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1/150 preliminary data december 2001 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. m7020r 32k x 68-bit entry network search engine features summary n 32k data entries in 68-bit mode n table may be partitioned into up to four (4) quadrants (data entry width in each octant is configurable as 34, 68, 136, or 272 bits.) n up to 83 million sustained searches per second in 68-bit and 136-bit configurations n up to 41.5 million searches per second in 34-bit and 272-bit configurations n searches any sub-field in a single cycle n offers bit-by-bit and global masking n synchronous, pipelined operation n up to 31 search engines cascadable without performance degradation n when cascaded, the database entries can scale from 248k to 1984k depending on the width of the entry n glueless interface to industry- standard srams n simple hardware instruction interface n ieee 1149.1 test acc ess port n operating supply voltages include: v dd (operating supply voltage) = 1.8v v ddq (operating supply voltage for i/o) = 2.5 or 3.3v n 272 pbga, 27mm x 27mm figure 1. 272-ball pbga package 272-ball pbga 27mm x 27mm
m7020r 2/150 table of contents description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 product range (table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 switch/router implementation using the m7020r (figure 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 signal names (table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 connections (figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 m7020r block diagram (figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 absolute maximum ratings (table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 dc and ac measurement conditions (table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 m7020r 2.5, or 3.3v ac testing load (figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 m7020r 2.5, or 3.3v input waveform (figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 m7020r 2.5, or 3.3v i/o output load equivalent (figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 capacitance (table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 dc characteristics (table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ac timing waveforms with clk2x (figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ac timing parameters with clk2x (table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 cmd bus and dq bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 database entry (data array and mask array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 arbitration logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 pipeline and sram control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 full logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 connection descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 clocks and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 cmd and dq bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 sram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 cascade interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 device identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 test access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 clocks (clk2x and phs_l) (figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0
3/150 m7020r registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 register overview (table 8.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 comparand registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 comparand register selection during search and learn instructions (figure 10.) . . . . . . . . . 22 addressing the global masks register array (figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 search-successful registers (ssr[0:7]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 search-successful register (ssr) description (table 9.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 the command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 command register field descriptions (table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 the information register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 information register field descriptions (table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 the read burst address register (rburreg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 the write burst address register (wburreg). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 the nfa register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 read burst register description (table 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 write burst register description (table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 nfa register (table 14.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 search engine architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 data and mask addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 m7020r database width configuration (figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 bit position match (table 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 multi-width configuration example (figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 m7020r data and mask array addressing (figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 command codes and parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 commands and command parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 command codes (table 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 command parameters (table 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 read command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 single location read cycle timing (figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 burst read of the data and mask arrays (blen = 4) (figure 16.) . . . . . . . . . . . . . . . . . . . . . . . . 31 read command parameters (table 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 data and mask array, sram read address format (table 19.) . . . . . . . . . . . . . . . . . . . . . . . . . . 32 read address format for internal registers (table 20.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 read address format for data and mask arrays (table 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 single location write cycle timing (figure 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 burst write of the data and mask arrays (blen = 4) (figure 18.). . . . . . . . . . . . . . . . . . . . . . . . 35 (single) write address format for data and mask arrays or sram (table 22.) . . . . . . . . . . . . . 35 write address format for internal registers (table 23.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 write address format for data and mask array (burst write) (table 24.) . . . . . . . . . . . . . . . . . . 36
m7020r 4/150 search command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 68-bit configuration with single device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 hardware diagram for a table with one device (figure 19.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 timing diagram for a 68-bit configuration search for one device (figure 20.) . . . . . . . . . . . . . 38 x68 table with one device (figure 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 latency of search from instruction to sram access cycle, 68-bit, 1 device (table 25.). . . . . . 39 shift of ssf and ssv from sadr (table 26.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 68-bit search on tables configured as x68 using up to eight m7020r devices. . . . . . . . . 40 hit/miss assumption (table 27.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 hardware diagram for a table with eight devices (figure 22.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 x68 table with eight devices (figure 23.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 timing diagrams for x68 using up to eight m7020r devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 68-bit search for device 0 (figure 24.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 68-bit search for device 1 (figure 25.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 68-bit search for device 7 (last device) (figure 26.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 latency of search from instruction to sram access cycle, 68-bit, up to 8 devices (table 28.) 46 shift of ssf and ssv from sadr (table 29.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 68-bit search on tables configured as x68 using up to 31 m7020r devices. . . . . . . . . . . 46 hit/miss assumption (table 30.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 hardware diagram for a table with 31 devices (figure 27.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 hardware diagram for a block of up to eight devices (figure 28.) . . . . . . . . . . . . . . . . . . . . . . . . 49 x68 table with 31 devices (figure 29.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 timing diagrams for x68 using up to 31 m7020r devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 each device in block number 0 (miss on each device) (figure 30.) . . . . . . . . . . . . . . . . . . . . 51 each device above the winning device in block number 1 (figure 31.) . . . . . . . . . . . . . . . . . 52 globally winning device in block number 1 (figure 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 devices below the winning device in block number 1 (figure 33.). . . . . . . . . . . . . . . . . . . . . 54 devices above the winning device in block number 2 (figure 34.) . . . . . . . . . . . . . . . . . . . . 55 globally winning device in block number 2 (figure 35.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 devices below the winning device in block number 2 (figure 36.). . . . . . . . . . . . . . . . . . . . . 57 devices above the winning device in block number 3 (figure 37.) . . . . . . . . . . . . . . . . . . . . 58 globally winning device in block number 3 (figure 38.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 devices below the winning device in block number 3 (not device 30 - last device) . . . . . . . 60 device 6 in block number 3 (device 30 in depth-cascaded table) (figure 40.) . . . . . . . . . . . 61 latency of search from instruction to sram access cycle, 68-bit, up to 31 devices . . . . . . . . 62 shift of ssf and ssv from sadr (table 32.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 136-bit configuration with single device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 hardware diagram for a table with 1 device (figure 41.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 timing diagram for a 136-bit search for one device (figure 42.). . . . . . . . . . . . . . . . . . . . . . . . 64 x136 table with one device (figure 43.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 latency of search from instruction to sram access cycle, 136-bit, 1 device (table 33.) . . . . . 65 shift of ssf and ssv from sadr (table 34.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5/150 m7020r 136-bit search on tables configured as x136 using up to eight m7020r devices . . . . . . . . 66 hit/miss assumption (table 35.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 hardware diagram for a table with eight devices (figure 44.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 x136 table with eight devices (figure 45.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 timing diagrams for x136 using up to eight m7020r devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 136-bit search for device number 0 (figure 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 136-bit search for device number 1 (figure 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 136-bit search for device number 7 (last device) (figure 48.) . . . . . . . . . . . . . . . . . . . . . . 71 latency of search from instruction to sram access cycle, 136-bit, up to 8 devices . . . . . . . . 72 shift of ssf and ssv from sadr (table 37.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 136-bit search on tables configured as x136 using up to 31 m7020r devices. . . . . . . . . . . 72 hit/miss assumption (table 38.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 hardware diagram for a table with 31 devices (figure 49.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 hardware diagram for a block of up to eight devices (figure 50.) . . . . . . . . . . . . . . . . . . . . . . . . 75 x136 table with 31 devices (figure 51.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 timing diagrams for x136 using up to 31 m7020r devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 each device in block number 0 (miss on each device) (figure 52.) . . . . . . . . . . . . . . . . . . . . 77 each device above the winning device in block number 1 (figure 53.) . . . . . . . . . . . . . . . . . 78 globally winning device in block number 1 (figure 54.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 devices below the winning device in block number 1 (figure 55.). . . . . . . . . . . . . . . . . . . . . 80 devices above the winning device in block number 2 (figure 56.) . . . . . . . . . . . . . . . . . . . . 81 globally winning device in block number 2 (figure 57.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 devices below the winning device in block number 2 (figure 58.). . . . . . . . . . . . . . . . . . . . . 83 devices above the winning device in block number 3 (figure 59.) . . . . . . . . . . . . . . . . . . . . 84 globally winning device in block number 3 (figure 60.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 devices below the winning device in block number 3 (not device 30 - last device) . . . . . . . 86 device 6 in block number 3 (device 30 in depth-cascaded table) (figure 62.) . . . . . . . . . . . 87 latency of search from instruction to sram access cycle, 136-bit, up to 31 devices . . . . . . . 88 shift of ssf and ssv from sadr (table 40.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 272-bit search on tables configured as x272 using a single m7020r device . . . . . . . . . . 88 hardware diagram for a table with one device (figure 63.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 timing diagram for a 272-bit search for one device (figure 64.). . . . . . . . . . . . . . . . . . . . . . . . 90 x272 table with one device (figure 65.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 latency of search from cycles c and d to sram access cycle, 272-bit, 1 device. . . . . . . . . . 91 shift of ssf and ssv from sadr (table 42.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 272-bit search on tables x272-configured using up to eight m7020r devices . . . . . . . . . 92 hit/miss assumption (table 43.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 hardware diagram for a table with eight devices (figure 66.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 x272 table with eight devices (figure 67.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 timing diagrams for x272-configured using up to eight m7020r devices . . . . . . . . . . . . . . . . . . 96 272-bit search for device number 0 (figure 68.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 272-bit search for device number 1 (figure 69.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 272-bit search for device number 7 (last device) (figure 70.) . . . . . . . . . . . . . . . . . . . . . . 98 latency of search from cycles c and d to sram access cycle, 272-bit, up to 8 devices . . . . 99 shift of ssf and ssv from sadr (table 45.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
m7020r 6/150 272-bit search on tables configured as x272 using up to 31 m7020r devices. . . . . . . . . . . 99 hit/miss assumption (table 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 hardware diagram for a table with 31 devices (figure 71.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 hardware diagram for a block of up to eight devices (figure 72.) . . . . . . . . . . . . . . . . . . . . . . . 102 x272 table with 31 devices (figure 73.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 03 timing diagrams for x272 using up to 31 m7020r devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 each device in block number 0 (miss on each device) (figure 74.) . . . . . . . . . . . . . . . . . . . 104 each device above the winning device in block number 1 (figure 75.) . . . . . . . . . . . . . . . . 105 globally winning device in block number 1 (figure 76.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 devices below the winning device in block number 1 (figure 77.). . . . . . . . . . . . . . . . . . . . 107 devices above the winning device in block number 2 (figure 78.) . . . . . . . . . . . . . . . . . . . 108 globally winning device in block number 2 (figure 79.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 devices below the winning device in block number 2 (figure 80.). . . . . . . . . . . . . . . . . . . . 110 devices above the winning device in block number 3 (figure 81.) . . . . . . . . . . . . . . . . . . . 111 globally winning device in block number 3 (figure 82.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 devices below the winning device in block number 3 (not device 30 - last device) . . . . . . 113 last device in block number 3 (device 30 in the table) (figure 84.) . . . . . . . . . . . . . . . . . . 114 latency of search from cycles c and d to sram access cycle, 272-bit, up to 31 devices . . 115 shift of ssf and ssv from sadr (table 48.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 mixed searches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 tables configured with different widths using an m7020r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 timing diagram for mixed search for one device (figure 85.) . . . . . . . . . . . . . . . . . . . . . . . . . 116 multi-width configurations example (figure 86.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 lram and ldev description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 learn command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 timing diagram of learn: tlsz = 00 (figure 87.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 timing diagram of learn: tlsz = 01 (except on the last device) (figure 88.). . . . . . . . . . . . . 120 timing diagram of learn on device 7: tlsz = 01 (figure 89.) . . . . . . . . . . . . . . . . . . . . . . . . . 121 latency of sram write cycle from second cycle of learn instruction (table 49.) . . . . . . . . 121 depth-cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 depth-cascading up to eight devices (one block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 depth-cascading up to 31 devices (4 blocks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 depth-cascading to generate a full signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 depth-cascading to form a single block (figure 90.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 depth-cascading four blocks (figure 91.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 full generation in a cascaded table (figure 92.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 sram addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 sram pio access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
7/150 m7020r sram read with a table of one device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 generating an sram bus address (table 50.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 sram read access for one device (figure 93.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 sram read with a table of up to eight devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table with eight devices (figure 94.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 sram read through device 0 in a block of eight devices (figure 95.). . . . . . . . . . . . . . . . . . . 130 sram read timing for device 7 in a block of eight devices (figure 96.) . . . . . . . . . . . . . . . . . 131 sram read with a table of up to 31 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table of 31 devices made of four blocks (figure 97.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 sram read through device 0 in a bank of 31 devices (device 0 timing) (figure 98.) . . . . . . 134 sram read through device 0 in a bank of 31 devices (device 30 timing) (figure 99.) . . . . . 135 sram write with a table of one device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 sram write access for one device (figure 100.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 sram write with a table of up to eight devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table with eight devices (figure 101.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 sram write through device 0 in a block of eight devices (figure 102.) . . . . . . . . . . . . . . . . . 140 sram write timing for device 7 in a block of eight devices (figure 103.). . . . . . . . . . . . . . . . 141 sram write with table(s) of up to 31 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table of 31 devices (four blocks) (figure 104.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 sram write through device 0 in a bank of 31 devices (device 0 timing) (figure 105.). . . . . 144 sram write through device 0 in a bank of 31 devices (device 30 timing) (figure 106.). . . . 145 jtag (1149.1) testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 supported operations (table 51.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 tap device id register (table 52.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
m7020r 8/150 description overview st microelectronics, inc.s m7020r search en- gine incorporates patent-pending associative pro- cessing technology? (apt) and is designed to be a high-performance, pipelined, synchronous, 32k-entry network database search engine. the m7020r database entry size can be 68 bits, 136 bits, or 272 bits. in the 68-bit entry mode, the size of the database is 32k entries. in the 136-bit mode, the size of the database is 16k entries, and in the 272-bit mode, the size of the database is 8k entries. the m7020r is configurable to support multiple databases with different entry sizes. the 34-bit entry table can be implemented using the global mask registers (gmrs) building-database size of 64k entries with a single device. performance the search engine can sustain 83 million transac- tions per second when the database is pro- grammed or configured as 68 or 136 bits. when the database is programmed to have an entry size of 34 or 272 bits, the search engine will perform at 41.5 million transactions per second. stms m7020r can be used to accelerate network proto- cols such as longest-prefix match (cidr), arp, mpls, and other layer 2, 3, and 4 protocols. applications this high-speed, high-capacity search engine can be deployed in a variety of networking and com- munications applications. the performance and features of the m7020r make it attractive in appli- cations such as enterprise lan switches and rout- ers and broadband switching and/or routing equipment supporting multiple data rates at ocC 48 and beyond. the search engine is designed to be scalable in order to support network database sizes to 1984k entries specifically for environ- ments that require large network policy databases. figure 4, page 11 shows the block diagram for the m7020r device. table 1. product range figure 2. switch/router implementation using the m7020r part number operating supply voltage operating i/o voltage speed temperature range m7020r-083za1 1.8v 2.5 or 3.3v 83mhz commercial m7020r-066za1 1.8v 2.5 or 3.3v 66mhz commercial m7020r-050za1 1.8v 2.5 or 3.3v 50mhz commercial program memory switch fabric switch processor network line interfaces system bus host asic sram bank search engine ai04272
9/150 m7020r table 2. signal names note: 1. signal types are: i = input only; i/o = input or output; o = output; and t = tristate 2. clk is an internal clock signal. any reference to clk cycles means one cycle of clk. 3. ack and eot signals require a weak, external pull-down resistor of 47 k w or 100 k w . symbol type (1) description clocks and reset clk2x i master clock phs_l i phase test i test input rst_l i reset command and dq bus cmd[8:0] i command bus cmdv i command valid dq[67:0] i/o address/data bus ack (4) t read acknowledge eot (4) t end of transfer ssf t search successful flag ssv t search successful flag valid sram interface sadr[21:0] t sram address ce_l t sram chip enable we_l t sram write enable oe_l t sram output enable ale_l t address latch enable cascade interface lhi[6:0] i local hit in lho[1:0] o local hit out bhi[2:0] i block hit in bho[2:0] o block hit out fuli[6:0] i full in fulo[1:0] o full out full o full flag device identification id[4:0] i device identification supplies v dd n/a chip core supply (1.8v) v ddq n/a chip i/o supply (2.5 or 3.3v) test access port tdi i test access ports test data in tck i test access ports test clock tdo t test access ports test data out tms i test access ports test mode select trst_l i test access ports reset
m7020r 10/150 figure 3. connections sadr 8 sadr 13 sadr 11 sadr 14 sadr 17 sadr 20 sadr 10 sadr 19 sadr 18 sadr 21 sadr 15 sadr 5 sadr 6 sadr 7 sadr 9 sadr 12 sadr 16 sadr 2 sadr 1 sadr 3 sadr 0 sadr 4 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd nc nc nc nc nc nc nc nc nc nc nc nc nc nc full eot nc nc nc nc ack nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc lhi6 lhi5 lhi4 lhi1 lho0 lho1 bhi0 bho0 bho1 bho2 fuli0 fuli3 fulo0 fulo1 fuli2 fuli1 fuli4 fuli5 fuli6 bhi2 bhi1 lhi0 lhi2 lhi3 nc nc nc nc nc nc nc nc nc v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd cmd8 cmd7 cmd5 cmd4 cmd3 cmd1 cmd6 cmd2 cmd0 cmdv dq17 dq15 dq13 dq11 dq9 dq1 dq5 dq7 dq21 dq27 dq31 dq33 dq29 dq25 dq23 dq19 dq35 dq37 dq43 dq53 dq57 dq61 dq63 dq67 dq59 dq55 dq49 dq64 dq62 dq60 dq66 dq58 dq56 dq50 dq48 dq46 dq44 dq42 dq38 dq30 dq36 dq32 dq34 dq28 dq20 dq24 dq22 dq16 dq18 dq8 dq0 dq2 dq4 dq12 dq10 dq14 dq6 dq26 dq40 dq52 dq54 dq51 dq45 dq41 dq39 dq47 dq65 dq3 tdo tms tck tdi id0 id2 id3 id1 id4 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd clk2x we_l oe_l ae_l ce_l phs_l ssf ssv rstl gnd t rst_l right bottom left top ai04270
11/150 m7020r figure 4. m7020r block diagram ai04271 comparand registers[15:0] global mask registers [7:0] information and command register burst read register burst write register next free address register search successful index registers [7:0] (all registers are 68-bit-wide) ta p controller pipeline and sram control arbitration logic command decode and pio access compare/pio data phs_l clk2x rst_l dq [67:0] cmd [8:0] cmdv ack eot cmd compare/pio data address decode priority encode match logic configurable as 64k x 34 32k x 68 16k x 136 8k x 272 data array configurable as 64k x 34 32k x 68 16k x 136 8k x 272 mask array full logic full [6:0] full fulo [1:0] id [4:0] lhi [6:0] bhi [2:0] ssf ssv lho [1:0] bho [2:0] ta p sadr [21:0] oe_l we_l ce_l ale_l
m7020r 12/150 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 3. absolute maximum ratings note: 1. soldering temperature not to exceed 260c for 10 seconds (total thermal budget not to exceed 150c for longer than 30 seconds). symbol parameter value unit t stg storage temperature (v dd off) C0 to 70 c t sld (1) lead solder temperature for 10 seconds 235 c v dd v dd operating supply voltage 1.9 v v ddq v ddq voltage for i/o (3.3v) 3.465 v v ddq v ddq voltage for i/o (2.5v) 2.6 v i o output current 200 ma p d power dissipation < 5 w
13/150 m7020r dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 4. dc and ac measurement conditions note: 1. maximum allowable applies to overshoot only (v ddq is 3.3v supply). 2. minimum allowable applies to undershoot only. sym parameter min max units v dd v dd operating supply voltage 1.7 1.9 v v ddq v ddq voltage for i/o (3.3v) 3.135 3.465 v v ddq v ddq voltage for i/o (2.5v) 2.4 2.6 v t a ambient operating temperature 0 70 c supply voltage tolerance C5 +5 % input pulse levels (v ddq = 3.3v) gnd to 3.0 v input pulse levels (v ddq = 2.5v) gnd to 2.5 v input rise and fall times at 0.3v and 2.7v (v ddq = 3.3v) 2ns (see figure 6, page 14) ns input rise and fall times at 0.25v and 2.25v (v ddq = 2.5v) 2ns (see figure 6, page 14) ns input timing reference levels (v ddq = 3.3v) 1.5 v input timing reference levels (v ddq = 2.5v) 1.25 v output timing reference levels (v ddq = 3.3v) 1.5 v output timing reference levels (v ddq = 2.5v) 1.25 v output load (see figure 5 and figure 7, page 14) v
m7020r 14/150 figure 5. m7020r 2.5, or 3.3v ac testing load figure 6. m7020r 2.5, or 3.3v input waveform figure 7. m7020r 2.5, or 3.3v i/o output load equivalent note: 1. output loading is specified with cl = 5pf as in figure 7. transition is measured at 200 mv from steady-state voltage. 2. the load used for v oh , v ol testing is shown in figure 7. c l v l = 1.25v for v ddq = 2.5v v l = 1.50v for v ddq = 3.3v 50 w z 0 = 50 w d out ac load ai05653 +2.5v v ddq = 2.5v / +3.0v v ddq = 3.3v 90% 10% 90% 10% gnd ai04299 208 w for v ddq = 2.5v 158 w for v ddq = 3.3v 192 w for v ddq = 2.5v 175 w for v ddq = 3.3v ai04266 5pf q v ddq for hi-z and v ol /v oh (1, 2)
15/150 m7020r table 5. capacitance note: 1. effective capacitance measured with power supply. sampled only, not 100% tested. 2. at 25c, f = 1mhz. 3. outputs deselected. table 6. dc characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v dd = 1.5v. symbol parameter test condition (1,2) min max unit c in input capacitance v in = 0v 6pf c io (3) output capacitance v out = 0v 6pf sym parameter test condition (1) min max unit i li input leakage current v ddq = v ddq (max), v in = 0 to v ddq (max) 10 a i lo output leakage current v ddq = v ddq (max), v in = 0 to v ddq (max) 10 a v il input low voltage (v ddq = 3.3v) C0.3 0.8 v v ih input high voltage (v ddq = 3.3v) 2.0 v ddq + 0.3 v v il input low voltage (v ddq = 2.5v) C0.3 0.7 v v ih input high voltage (v ddq = 2.5v) 1.7 v ddq + 0.3 v v ol output low voltage (v ddq = 3.3v) v ddq = v ddq (min), i ol = 8ma 0.4 v v oh output high voltage (v ddq = 3.3v) v ddq = v ddq (min), i oh = 8ma 2.4 v v ol output low voltage (v ddq = 2.5v) v ddq = v ddq (min), i ol = 8ma 0.4 v v oh output high voltage (v ddq = 2.5v) v ddq = v ddq (min), i oh = 8ma 2.0 v i dd1 1.8v supply current at v dd (max) 66mhz search rate 2300 ma 50mhz search rate 1800 ma i dd2 3.3v supply current at v dd (max) 66mhz search rate, i out = 0ma 200 ma 50mhz search rate, i out = 0ma 150 ma i dd2 2.5v supply current at v dd (max) 66mhz search rate, i out = 0ma 160 ma 50mhz search rate, i out = 0ma 120 ma
m7020r 16/150 figure 8. ac timing waveforms with clk2x cycle 1 cycle 0 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 12 cycle 9 cycle 11 clk2x signal group 0 signal group 2 signal group 3 signal group 4 signal group 5 clk ai04265 signal group 0: phs_l, rst_l signal group 1: dq, cmd, cmdv signal group 2: lhi, bhi, fuli signal group 3: lho, bho, fulo, full signal group 4: sadr, ce_l, oe_l, we_l, ale_l, ssf, ssv signal group 5: dq, ack, eot ticsch tckhov tckhsv tckhshz tckhslz tckhov tihch tisch tckhdz tckhdv signal group 1 tichch tihch tisch tisch tihch tihch
17/150 m7020r table 7. ac timing parameters with clk2x note: 1. valid for ambient operating temperature: t a = 0 to 70c; v dd = 1.8v. 2. values are based on 50% signal levels. 3. based on an ac load of cl = 30pf (see figure 5, figure 6, and figure 7, page 14). 4. these parameters are sampled and not 100% tested, and are based on an ac load of 5pf. row symbol m7020r-050 m7020r-066 m7020r-083 unit description (1) min max min max min max 1 f clock 100 133 166 mhz clk2x frequency 2 t clk 10 7.5 ns clk2x period 3 t ckhi 4.0 3.0 ns clk2x high pulse (2) 4 t cklo 4.0 3.0 ns clk2x low pulse (2 5 t isch 2.5 2.5 2.5 ns input setup time to clk2x rising edge. (2) 6 t ihch 0.6 0.6 0.6 ns input hold time to clk2x rising edge. (2) 7 t icsch 4.2 4.2 4.2 ns cascaded input setup time to clk2x rising edge. (2) 8 t ichch 0.6 0.6 0.6 ns cascaded input hold time to clk2x rising edge. (2) 9 t ckhov 9.5 8.5 ns rising edge of clk2x to lho, fulo, bho, full valid. (3) 10 t ckhdv 10.0 9.0 ns rising edge of clk2x to dq valid. (2) 11 t ckhdz 1.2 9.5 1.2 9.5 1.2 9.5 ns rising edge of clk2x to dq high-z. (4) 12 t ckhsv 10.0 9.0 ns rising edge of clk2x to sram bus valid. (2) 13 t ckhshz 7.0 6.5 ns rising edge of clk2x to sram bus high- z. (2,4) 14 t ckhslz 7.5 7.0 ns rising edge of clk2x to sram bus low- z. (2,4)
m7020r 18/150 operation the following subsections contain command (cmd and dq bus (command and databus), data- base entry, arbitration logic, pipeline, and sram control, and full logic descriptions. cmd bus and dq bus cmd[8:0] carries the cmd and its associated pa- rameter. dq[67:0] is used for data transfer to and from the database entries, which comprise a data and a mask field that are organized as data and mask arrays. the dq bus carries the search data (of the data and mask arrays and internal reg- isters) during the search command as well as the address and data during read and/or write operations. the dq bus can also carry the ad- dress information for the flow-through accesses to the external srams and/or ssrams. database entry (data array and mask array) each database entry comprises a data and a mask field. the resultant value of the entry is 1,' 0, or x (dont care), depending on the value in the data and mask bits. the on-chip priority encoder se- lects the first matching entry in the database that is nearest to location '0.' arbitration logic when multiple search engines are cascaded to create large databases, the data being searched is presented to all search engines simultaneously in the cascaded system. if multiple matches occur within the cascaded devices, arbitration logic on the search engines will enable the winning device (with a matching entry that is closest to address 0 of the cascaded database) to drive the sram bus. pipeline and sram control pipeline latency is added to give enough time to a cascaded systems arbitration logic to determine the device that will drive the index of the matching entry on the sram bus. pipeline logic adds laten- cy to both the sram access cycles and the ssf and ssv signals to align them to the host asic re- ceiving the associated data. full logic bit[0] in each of the 68-bit entries has a special purpose for the learn command (0 = empty, 1 = full). when all the data entries have bit[0] = 1, the database asserts the full flag, indicating all the search engines in the depth-cascaded array are full.
19/150 m7020r connection descriptions clocks and reset master clock (clk2x). m7020r samples all the data and control pins on the positive edge of clk2x. all signals are driven out of the device on the rising edge of clk2x (when phs_l is low). phase (phs_l). this signal runs at half the fre- quency of clk2x and generates an internal clk from clk2x see figure 9, page 20. test input (test - for cypress semiconductor use only). this signal should be connected to ground. reset (rst_l). driving rst_l low initializes the device to a known state. cmd and dq bus cmd bus (cmd[8:0]. [1:0] specifies the com- mand; [8:2] contains the cmd parameters. the descriptions of individual commands explains the details of the parameters. the encoding of com- mands based on the [1:0] field are: C 00: pio read C 01: pio write C 10: search C11: learn cmd valid ( cmdv) . qualifies the cmd bus: C 0: no command C 1: command address/data bus ( dq[67:0]) . this signal carries the read and write address and data during register, data, and mask array operations. it car- ries the compare data during search opera- tions. it also carries the sram address during sram pio accesses. read acknowledge (ack). this signal indi- cates that valid data is available on the dq bus during register, data, and mask array read oper- ations, or the data is available on the sram data bus during sram read operations. note: ack signals require a weak external pull- down resistor such as 47 or 100 k w . end of transfer (eot). this signal indicates the end of burst transfer to the data or mask array dur- ing read or write burst operations. note: eot signals require a weak external pull- down resistor such as 47 k w or 100 k w . search successful flag (ssf). when assert- ed, this signal indicates that the device is the glo- bal winner in a search operation. search successful flag valid (ssv). when asserted, this signal qualifies the ssf signal. sram interface sram address (sadr[21:0]). this bus con- tains address lines to access off-chip srams that contain associative data. see table 50, page 127 for the details of the generated sram address. in a database of multiple m7020rs, each corre- sponding bit of sadr from all cascaded devices must be connected. sram chip enable (ce_l). this is chip enable control for external srams. in a database of mul- tiple m7020rs, ce_l of all cascaded devices must be connected. this signal is then driven by only one of the devices. sram write enable (we_l). this is write en- able control for external srams. in a database of multiple m7020rs, we_l of all cascaded devices must be connected together. this signal is then driven by only one of the devices. sram output enable (oe_l). this is output en- able control for external srams. only the last de- vice drives this signal (with the lram bit set). address latch enable (ale_l). when this sig- nal is low, the addresses are valid on the sram address bus. in a database of multiple m7020rs, the ale_l of all cascaded devices must be con- nected. this signal is then driven by only one of the devices. cascade interface local hit in (lhi[6:0]). these pins depth-cas- cade the device to form a larger table size. one signal of this bus is connected to the lho[1] or lho[0] of each of the upstream devices in a block. all unused lhi pins are connected to a logic '0.' (for more information, see depth-cascading, page 122.) local hit out (lho[1:0]). lho[1] and lho[0] are the same logical signal. lho[1] or lho[0] is connected to one input of the lhi bus of up to four downstream devices in a block of up to eight de- vices. (for more information, see depth-cas- cading, page 122.) block hit in (bhi[2:0]). inputs from the previous bho[2:0] are tied to the bhi[2:0] of the current de- vice. in a four-block system, the last block can contain only seven devices because the id code 11111 is used for broadcast access. block hit out (bho[2:0]). these outputs from the last device in a block are connected to the bhi[2:0] inputs of the devices in the downstream blocks. full in (fuli[6:0]). each signal in this bus is con- nected to fulo[0] or fulo[1] of an upstream de- vice to generate the full signal for the depth- cascaded block.
m7020r 20/150 full out (fulo[1:0]). fulo[1] and fulo[0] are the same logical signal. one of these two signals must be connected to the fuli of up to four down- stream devices in a depth-cascaded table. bit [0] in the data array indicates if the entry is full (1) or empty (0).this signal is asserted if all of the bits in the data array are '1s.' refer to depth-cascading to generate a full signal, page 122. full flag (full). when asserted, this signal in- dicates that the table consisting of many depth- cascaded devices is full. device identification device identification (id[4:0]). the binary-en- coded device id for a depth-cascaded system starts at 00000 and goes up to 11110. 11111 is re- served for a special broadcast address that se- lects all cascaded search engines in the system. on a broadcast read-only, the device with the ldev bit set to '1' responds. supplies chip core supply (v dd ). this is equal to 1.8v. chip i/o supply (v ddq ). this is equal to either 2.5 or 3.3v. test access port test data in (tdi). this is the test access ports test data in. test clock (tck). this is the test access ports test clock. test data out (tdo). this is the test access ports test data out. test mode select (tms). this is the test ac- cess ports test mode select. test reset (trst_l). this is the test access ports test reset. clocks the m7020r receives the clk2x and phs_l sig- nals. it uses the phs_l signal to divide clk2x and generate an internal clock (clk), as shown in figure 9. the m7020r uses clk2x and clk for internal operations. figure 9. clocks (clk2x and phs_l) note: any reference to clk cycles means 1 cycle of the signal, clk. 1. clk is an internal signal. clk2x phs_l cl k (1) ai04750
21/150 m7020r registers all registers in the m7020r are 68 bits wide. the m7020r contains 8 pairs of comparand storage registers, 16 pairs of global mask registers (gmrs), eight search successful index registers and one each of cmd, information, burst read, burst write, and next-free address registers. ta- ble 8 provides an overview of all the m7020r reg- isters. the registers are ordered in ascending address order. each register group is then de- scribed in the following subsections. table 8. register overview address abbreviation type name 0C31 comp0C31 r 16 comparand registers. stores comparands from the dq bus for learning later. 32C47 masks rw 8 global mask registers array. 48C55 ssr0C7 r 8 search successful index registers. 56 command rw command register. 57 info r information register. 58 rburreg rw burst read register. 59 wburreg rw burst write register. 60 nfa r next free address register. 61C63 C C reserved
m7020r 22/150 comparand registers the device contains 32 68-bit comparand regis- ters (16 pairs) dynamically selected in every search operation to store the comparand pre- sented on the dq bus. the learn command will later use these registers when executed. the m7020r stores the search commands cycle a comparand in the even-numbered register and the cycle b comparand in the odd-numbered register, as shown in figure 10. mask registers the device contains 16 68-bit global mask regis- ters (8 pairs) dynamically selected in every search operation to select the search subfield. the addressing of these registers is explained in figure 11. the three-bit gmr index supplied on the cmd bus can apply 8 pairs of global masks during the search and write operations, as shown in figure 11. note: in 68-bit search and write operations, the host asic must program both the even and odd mask registers with the same values. each mask bit in the gmrs is used during search and write operations. in search op- erations, setting the mask bit to '1' enables com- pares; setting the mask bit to '0' disables compares (forced match) at the corresponding bit position. in write operations to the data or mask array, setting the mask bit to '1' enables writes; setting the mask bit to '0' disables writes at the corresponding bit position. figure 10. comparand register selection during search and learn instructions figure 11. addressing the global masks register array 13 5 0 68 68 1 0 3 2 5 4 7 6 30 31 0 15 1 a ddre ss index ai04275 13 5 0 68 68 1 0 3 2 5 4 7 6 9 8 11 10 13 12 15 14 0 1 6 7 2 5 4 3 a ddre ss index ai04276 search and write command global mask selection
23/150 m7020r search-successful registers (ssr[0:7]) the device contains eight search successful reg- isters (ssrs) to hold the index of the location where a successful search occurred. the format of each register is described in table 9. the search command specifies which ssr stores the index of a specific search command in cy- cle b of the search instruction. subsequently, the host asic can use this register to access that data array, mask array, or external sram using the index as part of the indirect access address (see table 19, page 32 and table 22, page 35) . the device with a valid bit set performs a read or write operation. all other devices suppress the operation. table 9. search-successful register (ssr) description field range initial value description index [14:0] x index. this is the address of the 68-bit entry where a successful search occurs. the device updates this field only when a search is successful. if a hit occurs in a 136-bit entry-size quadrant, the lsb is '0.' if a hit occurs in a 272-bit entry size quadrant, the two lsbs are '00.' this index updates if the device is either a local or global winner in a search operation. C [30:15] 0 reserved. valid [31] 0 valid. during search operation in a depth-cascaded configuration, the device that is a global winner in a match sets this bit to '1.' this bit updates only when the device is a global winner in a search operation. C [67:32] 0 reserved.
m7020r 24/150 the command register table 10. command register field descriptions field range initial value description srst [0] 0 software reset. if '1,' this bit resets the device, with the same effect as the hardware reset. internally, it generates a reset pulse lasting for eight clk cycles. this bit automatically resets to a '0' the reset cycle has completed. deve [1] 0 device enable. if '0,' it keeps the sram bus (sadr, we_l, ce_l, oe_l, and ale_l), ssf, and ssv signals in 3-state condition and forces the cascade interface output signals lho[1:0] and bho[2:0] to '0.' it also keeps the dq bus in input mode. the purpose of this bit is to make sure that there are no bus contentions when the devices power up in the system. tlsz [3:2] 01 table size. the host asic must program this field to configure the chips into a table of a certain size. this field affects the pipeline latency of the search and learn operations as well as the read and write accesses to the sram (sadr[21:0], ce_l, oe_l, we_l, ale_l, ssv, ssf, and ack). once programmed, the search latency stays constant. tlsz [3:2] 01 latency in # of clk cycles 00: 1 device 4 01: 2-8 devices 5 10: 9-31 devices 6 11: reserved hlat [6:4] 000 latency of hit signals. this field adds latency to the ssf and ssv signals during search, and ack signal during sram read access by the following number of clk cycles. 000: 0 100: 4 001: 1 101: 5 010: 2 110: 6 011: 3 111: 7 ldev [7] 0 last device in the cascade. when set, this device is the last device on the sram bus in the depth-cascaded table and is the default driver for the ssf and ssv signals. in the event of a search failure, the device with this bit set drives the hit signals as follows: ssf = 0, ssv = 1 during non-search cycles, the device with this bit set drives the signals as follows: ssf = 0, ssv = 0 lram [8] 0 last device on this sram bus. when set, this device is the last device on this sram bus in the depth-cascaded table and is the default driver for the sadr, ce_l, we_l, and ale_l signals. in cycles where no m7020r device in a depth-cascaded table drives these signals, this device drives the signals as follows: sadr = 3fffff, ce_l = 1 we_l = 1 ale_l = 1 oe_l is always driven by the device for which this bit is set.
25/150 m7020r the information register table 11. information register field descriptions note: 1. this field may change in future versions. cfg [16:9] 0000 0000 database configuration. the device is internally divided into four quadrants of 8k x 68, each of which can be configured as 8k x 68, 4k x 136, or 2k x 272 as follows: 00: 8k x 68 01: 4k x 136 10: 2k x 272 11: reserved bits [10:9] apply to configuring the 1st quadrant in the address space. bits [12:11] apply to configuring the 2nd quadrant in the address space. bits [14:13] apply to configuring the 3rd quadrant in the address space. bits [16:15] apply to configuring the 4th quadrant in the address space. [67:17] 0 reserved. field range initial value description field range initial value description revision [3:0] 0001 (1) revision number. this is the current device revision number. numbers start from one and increment by one for each revision of the device. implementation [6:4] 001 this is the m7020r implementation number. reserved [7] 0 reserved. device id [11:8] 0001 or 0010 this is the device identification number. device id [12] reserved device id [15:13] 00000100 this is the device identification number. mfid [31:16] 1101_1100_0111_1111 manufacturer id. this field is the same as the manufacturer id and continuation bits in the tap controller. [67:32] reserved.
m7020r 26/150 the read burst address register (rburreg) these read burst address register fields must be programmed before burst read (see table 12). the write burst address register (wburreg) these write burst address register fields must be programmed before burst write (see table 13). the nfa register bit [0] of each 68-bit data entry is a special bit des- ignated for use in the operation of the learn command. in 68-bit quadrants, the bit[0] indicates whether a location is full (bit set to '1') or empty (bit set to '0'). every write/learn command loads the address of first 68-bit location that contains a '0' in the entrys bit[0]. this is stored in the nfa register (see table 14). if all the bits in a device are set to '1,' the m7020r asserts fulo[1:0] to '1.' in 136-bit-configured quadrants, the lsb of this register is always set to '0.' the host asic must set bit '0' and bit 68in a 136-bit word to either '0' or '1' to indicate full/empty status. note: both bits (0 and 68) must be set to '0' or '1' (e.g., '10' or '01' settings are invalid). table 12. read burst register description table 13. write burst register description table 14. nfa register field range initial value description adr [14:0] 0 address. this is the starting address of the data array or mask array during a burst read operation. it automatically increments by 1 for each successive read of the data array or mask array. once the operation is complete, the contents of this field must be reinitialized for the next operation. [18:15] reserved. blen [27:19] 0 length of burst access. the device is capable of writing from 4 up to 511 locations in a single burst. the blen decrements automatically. once the operation is complete, the contents of this field must be reinitialized for the next operation. [67:28] reserved. field range initial value description adr [14:0] 0 address. this is the starting address of the data array or mask array during a burst write operation. it automatically increments by 1 for each successive write of the data array or mask array. once the operation is complete, the contents of this field must be reinitialized for the next operation. [18:15] reserved. blen [27:19] 0 length of burst access. the device is capable of writing from 4 up to 511 locations in a single burst. the blen decrements automatically. once the operation is complete, the contents of this field must be reinitialized for the next operation. [67:28] reserved. address 67 - 15 14 - 0 60 reserved index
27/150 m7020r search engine architecture the m7020r consists of 32k x 68-bit storage cells referred to as data bits. there is a mask cell corre- sponding to each data cell. figure 12 shows the three organizations of the device based on the val- ue of the cfg bits in the command register. during a search operation, the search data bit (s), data array bit (d), mask array bit (m) and the global mask bit (g) are used in the following man- ner to generate a match at that bit position (see table 15, page 28). the entry with all matched bit positions results in a successful search during a search operation. in order for a successful search within a device to make the device the local winner in the search operation, all 68-bit positions must generate a match for a 68-bit entry in 68-bit-configured quad- rants, or all 136-bit positions must generate a match for two consecutive even and odd 68-bit en- tries in quadrants configured as 136 bits, or all 272-bit positions must generate a match for 4 con- secutive entries aligned to 4 entry-page bound- aries of 68-bit entries in quadrants configured as 272 bits. an arbitration mechanism using a cascade bus de- termines the global winning device among the lo- cal winning devices in a search cycle. the global winning device drives the sram bus, ssv, and the ssf signals. in case of a search failure, the devices with the ldev and lram bits set drive(s) the sram bus, ssf, and ssv signals. the m7020r device can be configured to contain tables of different widths, even within the same chip. figure 13, page 28 shows a sample configu- ration of different widths. data and mask addressing figure 14, page 28 shows the m7020r data array and mask array addressing procedure. figure 12. m7020r database width configuration data data data masks masks masks 32 k cfg = 00000000 cfg = 01010101 cfg = 10101010 68 136 272 16 k 8 k ai04279
m7020r 28/150 table 15. bit position match figure 13. multi-width configuration example figure 14. m7020r data and mask array addressing g m d s match 0xxx1 10xx1 11001 11100 11010 11111 8 k 8 k 4 k 2 k 68 68 136 272 cfg = 10010000 ai04280 cfg = 0 000 00 00 cfg = 10101010 67 0 0 1 2 3 32 76 7 27 1 0 3 2 1 0 7 6 5 4 3 27 64 3 276 5 327 66 3 27 67 68 cfg = 010 10 10 1 135 0 1 0 3 2 5 4 7 6 32766 32767 (6 8-bit co nfigu ration ) (27 2-bit conf ig urat io n) (1 36 -b it con figura tion) 32 k 8k 16 k 68 68 68 68 68 68 ai04281
29/150 m7020r command codes and parameters a master device, such as an asic controller, is- sues commands to the m7020r using the com- mand valid cmdv signal and the cmd bus. the following subsections describe the functions of the commands. command codes the m7020r implements four basic commands shown in table 16. the command code must be presented to cmd[1:0] while keeping the com- mand valid (cmdv) signal high for two clk2x cy- cles. these two clk2x cycles are designated as cycle a and cycle b. the controller asic must align the instructions with the phs_l signal. the cmd[8:2] field passes the parameters of the com- mand in cycles a and b. commands and command parameters table 17, page 29 lists the cmd bus fields that contain the m7020r command parameters as well as their respective cycles. table 16. command codes table 17. command parameters note: 1. the 272-bit-configured devices or 272-bit-configured quadrants within devices do not support the learn instruction. cmd code command description 00 read reads one of the following: data array, mask array, device registers, or external sram. 01 write writes one of the following: data array, mask array, device registers, or external sram. 10 search searches the data array for a desired pattern using the specified register from the global mask register array and local mask associated with each data cell. 11 learn the device has internal storage for up to 16 comparands that it can learn. the device controller can insert these entries at the next free address (as specified by the nfa register) using the learn instruction. cmd cyc 8 7 6 5 4 3 2 1 0 read a sadr[21] sadr[20] x 0 0 0 0 = single 1 = burst 00 b0 0 0 000 0 = single 1 = burst 00 write a sadr[21] sadr[20] x global mask register index [2:0] 0 = single 1 = burst 01 b0 0 0 global mask register index [2:0] 0 = single 1 = burst 01 search a sadr[21] sadr[20] sadr[19] global mask register index [2:0] 68-bit or 136-bit: 0 272-bit: 1 in 1st cycle 0 in 2nd cycle 10 b successful search register index[2:0] comparand register index 1 0 learn (1) a sadr[21] sadr[20] x comparand register index 1 1 b0 0 mode 0: 68-bit 1: 136-bit comparand register index 1 1
m7020r 30/150 read command the read can be a single read of a data array, a mask array, an sram, or a register location (cmd[2] = 0). it can be a burst read (cmd[2] = 1) or mask array locations using an internal auto-in- crementing address register (rburadr). table 18, page 32 describes each type of read com- mand. a single-location read operation lasts six cycles, as shown in figure 15, page 31. the burst read adds two cycles for each successive read. the sadr[21:20] bits supplied in the read instruction cycle a drive sadr[21:20] signals during the read of an sram location. the single read operation takes six clk cycles, in the following sequence: C cycle 1: the host asic applies the read in- struction on the cmd[1:0] (cmd[2] = 0), using cmdv = 1, and the dq bus supplies the ad- dress, as shown in table 19, page 32 and table 20, page 33. the host asic selects the m7020r for which id[4:0] matches the dq[25:21] lines. if the dq[25:21] = 11111, the host asic selects the m7020r with the ldev bit set. the host asic also supplies sadr[21:20] on cmd[8:7] in cycle a of the read instruction if the read is directed to the external sram. C cycle 2: the host asic floats dq[67:0] to 3- state condition. C cycle 3: the host asic keeps dq[67:0] in 3- state condition. C cycle 4: the selected device starts to drive the dq[67:0] bus and drives the ack signal from z to low. C cycle 5: the selected device drives the read data from the addressed location on the dq[67:0] bus and drives the ack signal high. C cycle 6: the selected device floats dq[67:0] to 3-state condition and drives the ack signal low. at the termination of cycle 6, the selected device releases the ack line to 3-state condition. the read instruction is complete, and a new opera- tion can begin. note: the latency of the sram read will be dif- ferent than the one described above (see sram pio access, page 126). table 19, page 32 lists and describes the format of the read address for a data array, mask array, or sram. in a burst read operation, the read lasts 4 + 2n clk-cycles (where n stands for the number of accesses in the burst specified by the blen field of the rburreg). table 20, page 33 describes the read address format for the internal registers. figure 16, page 31 illustrates the timing diagram for the burst read of the data or mask array. this operation assumes that the host asic has pro- grammed the rburreg with the starting address (adr) and the length of transfer (blen) before ini- tiating the burst read command. C cycle 1: the host asic applies the read in- struction on the cmd[1:0] (cmd[2] = 1), using cmdv=1 and the address supplied on the dq bus, as shown in table 21, page 33. the host asic selects the m7020r for which id[4:0] matches the dq[25:21] lines. if the dq[25:21] = 11111, the host asic selects the m7020r with the ldev bit set. C cycle 2: the host asic floats dq[67:0] to the 3- state condition. C cycle 3: the host asic keeps dq[67:0] in the 3-state condition. C cycle 4: the selected device starts to drive the dq[67:0] bus and drives ack and eot from z to low. C cycle 5: the selected device drives the read data from the addressed location on the dq[67:0] bus and drives the ack signal high. note: cycles four and five repeat for each addi- tional access until all the accesses specified in the burst length (blen) field of rburreg are complete. on the last transfer, the m7020r drives the eot signal high. C cycle (4 + 2n): the selected device drives the dq[67:0] to 3-state condition and drives the ack and the eot signals low. at the termination of cycle 4 + 2n, the selected de- vice floats the ack line to 3-state condition. the burst read instruction is complete, and a new op- eration can begin (see table 21, page 33 for burst read address formats).
31/150 m7020r figure 15. single location read cycle timing figure 16. burst read of the data and mask arrays (blen = 4) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 clk2x cmdv cmd[1:0] ack dq phs_ l ai04672 read cmd[8:2] b a ad dress ff data cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 11 cycle 12 cycle 9 clk2x cmdv cmd[1:0] cmd[8:2] ack eot dq phs_ l ai04283 read b a ad dress ff data0 ff data1 ff data2 ff data3
m7020r 32/150 table 18. read command parameters table 19. data and mask array, sram read address format note: 1. | stands for logical or operation. { } stands for concatenation operator. cmd parameter cmd[2] read command description 0 single read reads a single location of the data array, mask array, external sram, or device registers. all access information is applied on the dq bus. 1 burst read reads a block of locations from the data array or mask array as a burst. the internal register (rburadr) specifies the starting address and the length of the data transfer from the data array or mask array, and it auto-increments the address for each access. all other access information is applied on the dq bus. note: the device registers and external sram can only be read in single-read mode. dq [67:30] dq [29] dq [28:26] dq [25:21] dq [20:19] dq [18:15] dq [14:0] reserved 0: direct 1: indirect successful search register index (applicable if dq[29] is indirect) id 00: data array reserved if dq[29] is '0,' this field carries address of data array location. if dq[29] is '1,' the successful search register id (ssri) specified on dq[28:26] supplies the address of the data array location: {ssr[14:2], ssr[1] | dq[1], ssr[0] | dq[0]} (1) reserved 0: direct 1: indirect successful search register index (applicable if dq[29] is indirect) id 01: mask array reserved if dq[29] is '0,' this field carries address of mask array location. if dq[29] is '1,' the successful search register id (ssri) specified on dq[28:26] supplies the address of the mask array location: {ssr[14:2], ssr[1] | dq[1], ssr[0] | dq[0]} (1) reserved 0: direct 1: indirect successful search register index (applicable if dq[29] is indirect) id 10: external sram reserved if dq[29] is '0,' this field carries address of sram location. if dq[29] is '1,' the successful search register id (ssri) specified on dq[28:26] supplies the address of the sram location: {ssr[14:2], ssr[1] | dq[1], ssr[0] | dq[0]} (1)
33/150 m7020r table 20. read address format for internal registers table 21. read address format for data and mask arrays write command the write can be a single write of a data array, mask array, register, or external sram location (cmd[2] = 0). it can be a burst write (cmd[2] = 1) using an internal auto-incrementing address register (wburadr) of the data array or mask array locations. a single-location write is a three-cycle operation, shown in figure 17, page 34. the burst write adds one extra cycle for each successive write. the write operation sequence is as follows: C cycle 1a: the host asic applies the write in- struction on the cmd[1:0] (cmd[2] = 0), using cmdv=1 and the address supplied on the dq bus, as shown in table 22, page 35. the host asic also supplies the index to the global mask register to mask the write to the data array or mask array location in cmd[5:3]. for sram writes, the host asic must supply the sadr[21:20] on cmd[8:6]. the host asic sets cmd[9] to '0' for the normal write. C cycle 1b: the host asic continues to apply the write instruction to the cmd[1:0] (cmd[2] = 0), using cmdv = 1 and the address supplied on the dq bus. the host asic contin- ues to supply the global mask register index to mask the write to the data or mask array loca- tions in cmd[5:3]. the host asic selects the device where id[4:0] matches the dq[25:21] lines, or it selects all the devices when dq[25:21] = 11111. C cycle 2: the host asic drives the dq[67:0] with the data to be written to the data array, mask array, external sram, or register location of the selected device. C cycle 3: idle cycle. at the termination of this cy- cle, another operation can begin. note: the latency of the sram write will be different than the one described above (see sram pio access, page 126). the burst write operation lasts for n + 2 clk cy- cles (where n signifies the number of accesses in the burst as specified in the blen field of the wburreg register, please see figure 18, page 35). this operation assumes that the host asic has programmed the wburreg with the starting ad- dress (adr) and the length of transfer (blen) be- fore initiating the burst write command (see table 24, page 36 for format). the sequence is as fol- lows: C cycle 1a: the host asic applies the write in- struction on the cmd[1:0] (cmd[2] = 1), using cmdv = 1 and the address supplied on the dq bus, as shown in table 24, page 36. the host asic also supplies the index to the global mask register to mask the write to the data or mask ar- ray locations in cmd[5:3]. C cycle 1b: the host asic continues to apply the write instruction on the cmd[1:0] (cmd[2] = 0), using cmdv = 1 and the address supplied on the dq bus. the host asic contin- ues to supply the global mask register index to mask the write to the data or mask array loca- tions in cmd[5:3]. the host asic selects the device where id[4:0] matches the dq[25:21] lines, or it selects all the devices when dq[25:21] = 11111. dq[67:26] dq[25:21] dq[20:19] dq[18:6] dq[5:0] reserved id 11: register reserved register address dq[67:26] dq[25:21] dq[20:19] dq[18:15] dq[14:0] reserved id 00: data array reserved do not care. these 15 bits come from the internal register (rburadr) which increments for each access. reserved id 01: mask array reserved do not care. these 16 bits come from the internal register (rburadr) which increments for each access.
m7020r 34/150 C cycle 2: the host asic drives the dq[67:0] with the data to be written to the data array or mask array location of the selected device. the m7020r writes the data from the dq[67:0] bus only to the subfield that has the corresponding mask bit set to '1' in the global mask register specified by the index cmd[5:3] and supplied in cycle 1. C cycles 3 to n + 1: the host asic drives the dq[67:0] with the data to be written to the next data array or mask array location (addressed by the auto-increment adr field of the wburreg register) of the selected device. the m7020r writes the data on the dq[67:0] bus only to the subfield that has the correspond- ing mask bit set to '1' in the global mask register specified by the index cmd[5:3] and supplied in cycle 1. the m7020r drives the eot signal low from cycle 3 to cycle n; the m7020r drives the eot signal high in cycle n + 1 (n is specified in the blen field of the wburreg). C cycle n + 2: the m7020r drives the eot signal low. at the termination of the cycle n + 2, the m7020r floats the eot signal to a 3-state, and a new instruction can begin. figure 17. single location write cycle timing cycle 1 cycle 2 cycle 3 cycle 4 cycle 0 clk2x cmdv cmd[1:0] dq phs_ l ai04284 write cmd[8:2] b a ad dress data x
35/150 m7020r figure 18. burst write of the data and mask arrays (blen = 4) table 22. (single) write address format for data and mask arrays or sram note: 1. | stands for logical or operation. { } stands for concatenation operator. dq [67:30] dq [29] dq [28:26] dq [25:21] dq [20:19] dq [18:15] dq [14:0] reserved 0: direct 1: indirect successful search register index (applicable if dq[29] is indirect) id 00: data array reserved if dq[29] is '0,' this field carries the address of the data array location. if dq[29] is '1,' the successful search register specified by dq[28:26] supplies the address of the data array location: {ssr[14:2], ssr[1] | dq[1], ssr[0] | dq[0]} (1) reserved 0: direct 1: indirect successful search register index (applicable if dq[29] is indirect) id 01: mask array reserved if dq[29] is '0,' this field carries address of the mask array location. if dq[29] is '1,' the successful search register specified by dq[28:26] supplies the address of the mask array location: {ssr[14:2], ssr[1] | dq[1], ssr[0] | dq[0]} (1) reserved 0: direct 1: indirect successful search register index (applicable if dq[29] is indirect) id 10: external sram reserved if dq[29] is '0,' this field carries address of the data sram location. if dq[29] is '1,' the successful search register specified by dq[28:26] supplies the address of the sram location: {ssr[14:2], ssr[1] | dq[1], ssr[0] | dq[0]} (1) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 clk2x cmdv cmd[1:0] eot dq phs_ l ai04285 write cmd[8:2] b a ad dress data0 data1 data2 data3 x
m7020r 36/150 table 23. write address format for internal registers table 24. write address format for data and mask array (burst write) search command the m7020r (silicon) search engine can be con- figured in ten ways: C 68-bit search on tables configured as x68 using one device C 68-bit search on tables configured as x68 using up to 8 devices C 68-bit search on tables configured as x68 using up to 31 devices C 136-bit search on tables configured as x136 using one device C 136-bit search on tables configured as x136 using up to 8 devices C 136-bit search on tables configured as x136 using up to 31 devices C 272-bit search on tables configured as x272 using one devices C 272-bit search on tables configured as x272 using up to 8 devices C 272-bit search on tables configured as x272 using up to 31 devices C mixed-sizes on tables configured with differ- ent widths using an m7020r 68-bit configuration with single device the hardware diagram of the search subsystem of a single device is shown in figure 19. figure 20, page 38 shows the timing diagram for a search operation in the 68-bit configuration (cfg = 00000000) for one set of parameters. this illustra- tion assumes that the host asic has programmed tlsz to '00,' hlat to '000,' lram to '1,' and ldev to '1' in the command register. the following is the sequence of operations for a single 68-bit search command. C cycle a: the host asic drives cmdv high and applies the search command code ('10') on cmd[1:0] signals. cmd[5:3] must be driven with the index to the global mask register pair for use in the search operation. cmd[8:7] signals must be driven with the same bits that will be driven on sadr[21:20] by this device if it has a hit. dq[67:0] must be driven with the 68-bit data to be compared. the cmd[2] signal must be driven to logic '0.' C cycle b: the host asic continues to drive cmdv high and applies the search command ('10') on cmd[1:0]. cmd[5:2] must be driven by the index of the comparand register pair for stor- ing the 136-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching en- try and the hit flag (see search-successful registers (ssr[0:7]), page 23). the dq[67:0] continues to carry the 68-bit data to be com- pared. note: in the 68-bit configuration, the host asic must supply the same data on dq[67:0] during both cycles a and b. the even and odd pair of gmrs selected for the comparison must be pro- grammed with the same value. dq[67:26] dq[25:21] dq[20:19] dq[18:6] dq[5:0] reserved id 11: register reserved register address dq [67:26] dq [25:21] dq [20:19] dq [18:15] dq [14:0] reserved id 00: data array reserved dont care. these 15 bits come from the internal register (wburadr), which increments with each access. reserved id 01: mask array reserved dont care. these 15 bits come from the internal register (wburadr), which increments with each access.
37/150 m7020r the logical 68-bit search operation is shown in figure 21, page 39. the entire table consisting of 68-bit entries is compared to a 68-bit word k (pre- sented on the dq bus in both cycles a and b of the command) using the gmr and the local mask bits. the effective gmr is the 68-bit word speci- fied by the identical value in both even and odd gmr pairs selected by the gmr index in the com- mands cycle a. the 68-bit word k (presented on the dq bus in both cycles a and b of the com- mand) is also stored in both even and odd com- parand register pairs selected by the comparand register index in the commands cycle b. in a x68 configuration, only the even comparand register can be subsequently used by the learn com- mand. the word k (presented on the dq bus in both cycles a and b of the command) is compared with each entry in the table starting at location 0. the first matching entrys location address, l, is the winning address that is driven as part of the sram address on the sadr[21:0] lines (see sram addressing, page 126). the search command is a pipelined operation and executes a search at half the rate of the fre- quency of clk2x for 68-bit searches in x68-con- figured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 68-bit search command cycle (two clk2x cycles) is shown in table 25, page 39. the latency of a search from command to sram access cycle is 4 for a single device in the table and tlsz = 00. in addition, ssv and ssf shift further to the right for different values of hlat, as specified in table 26, page 39. figure 19. hardware diagram for a table with one device dq[67:0] cmdv, cmd[8:0] ssf, ssv sram bhi[2:0] bhi[2:0] lho[1] lhi 3210 m7020r lho[0] 654 ai05664
m7020r 38/150 figure 20. timing diagram for a 68-bit configuration search for one device cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[8:2] phs_ l ale_l ai04286 a b a b a b a b dq d1 d2 d3 a1 a3 d4 search3 hit search4 miss search1 hit search2 miss cfg = 00000000, hlat = 000, tlsz = 00, lram = 1, ldev = 1 search1 search2 search3 search4 01 01 01 01 1 1 1 1 1 0 0 0 1 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0
39/150 m7020r figure 21. x68 table with one device table 25. latency of search from instruction to sram access cycle, 68-bit, 1 device table 26. shift of ssf and ssv from sadr # of devices max table size latency in clk cycles 1 (tlsz = 00) 32k x 68-bit 4 2C8 (tlsz = 01) 256k x 68-bit 5 9C31 (tlsz = 10) 992k x 68-bit 6 hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 comparand register (even) comparand register (odd) 67 0 k cfg = 00000000 0 1 2 3 32767 (68-bit configuration) location address l k comparand register (even) 67 0 k gmr 67 0 ai05665 (first matching entry)
m7020r 40/150 68-bit search on tables configured as x68 using up to eight m7020r devices the hardware diagram of the search subsystem of eight devices is shown in figure 22, page 41. the following are the parameters programmed into the eight devices: C first seven devices (device 0C6): cfg = 00000000, tlsz = 01, hlat = 010, lram = 0, and ldev = 0. C eighth device (device 7): cfg = 00000000, tlsz = 01, hlat = 010, lram = 1, and ldev = 1. note: all eight devices must be programmed with the same values for tlsz and hlat. only the last device in the table (device 7 in this case) must be programmed with lram = 1 and ldev = 1. all other upstream devices (devices 0 through 6 in this case) must be programmed with lram = 0 and ldev = 0. figure 24, page 43 shows the timing diagram for a search command in the 68-bit-configured table of eight devices for device 0. figure 25, page 44 shows the timing diagram for a search com- mand in the 68-bit-configured table of eight devic- es for device 1. figure 26, page 45 shows the timing diagram for a search command in the 68-bit-configured table of eight devices for device 7 (the last device in this specific table). for these timing diagrams four 68-bit searches are per- formed sequentially. hit/miss assumptions were made as shown below in table 27. the sequence of operation for a 68-bit search command is as follows:] C cycle a: the host asic drives cmdv high and applies the search command code ('10') on cmd[1:0] signals. cmd[5:3] must be driven with the index to the global mask register pair for use in the search operation. cmd[8:7] signals must be driven with the same bits that will be driven on sadr[23:21] by this device if it has a hit. dq[67:0] must be driven with the 68-bit data to be compared. the cmd[2] signal must be driven to logic '0.' C cycle b: the host asic continues to drive cmdv high and applies the search command ('10') on cmd[1:0]. cmd[5:2] must be driven by the index of the comparand register pair for stor- ing the 136-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching en- try and the hit flag (see search-successful registers (ssr[0:7]), page 23). the dq[67:0] continues to carry the 68-bit data to be com- pared. note: for 68-bit searches, the host asic must supply the same data on dq[67:0] during both cycles a and b. the even and odd pair of gmrs selected for the comparison must be pro- grammed with the same value. the logical 68-bit search operation is shown in figure 23, page 42. the entire table with eight de- vices of 68-bit entries is compared to a 68-bit word k (presented on the dq bus in both cycles a and b of the command) using the gmr and the local mask bits. the effective gmr is the 68-bit word specified by the identical value in both even and odd gmr pairs in each of the eight devices and selected by the gmr index in the commands cy- cle a. the 68-bit word k (presented on the dq bus in both cycles a and b of the command) is also stored in both even and odd comparand register pairs (selected by the comparand register index in command cycle b) in each of the eight devices. in the x68 configuration, only the even comparand register can subsequently be used by the learn command in one of the devices (only the first non- full device). the word k (presented on the dq bus in both cycles a and b of the command) is com- pared with each entry in the table starting at loca- tion 0. the first matching entrys location address, l, is the winning address that is driven as part of the sram address on the sadr[21:0] lines (see sram addressing, page 126). the global winning device will drive the bus in a specif- ic cycle. on a global miss cycle the device with lram = 1 (default driving device for the sram bus) and ldev = 1 (default driving device for ssf and ssv si gnals) will be the default driver for such missed cycles. the search command is a pipelined operation and executes a search at half the rate of the fre- quency of clk2x for 72-bit searches in x68-con- figured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 68-bit search command cycle (two clk2x cycles) is shown in table 28, page 46 the latency of the search from command to sram access cycle is 5 for up to eight devices in the table (tlsz = 01). ssv and ssf also shift further to the right for different values of hlat, as specified in table 29, page 46.
41/150 m7020r table 27. hit/miss assumption figure 22. hardware diagram for a table with eight devices search number1234 device 0 hit miss hit miss device 1 miss hit hit miss device 2-6 miss miss miss miss device 7 miss miss hit hit sram bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bho[2] bho[1] bho[0] bho[2] bho[1] bho[0] lho[1] lho[0] lho[0] lho[1] lho[0] lho[0] lho[0] lho[0] lho[0] lho[1] lho[1] lho[1] lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi 3210 3210 3210 3210 3210 3210 3210 3210 m7020r #0 m7020r #1 m7020r #2 m7020r #3 m7020r #4 m7020r #5 m7020r #6 m7020r #7 lho[0] 654 654 654 654 654 654 654 654 ai05666 ssf, ssv dq[67:0] cmdv cmd[8:0]
m7020r 42/150 figure 23. x68 table with eight devices comparand register (even) comparand register (odd) 67 0 k cfg = 00000000 0 1 2 3 262148 (68-bit configuration) location address l k must be the same in each of the eight devices will be the same in each of the eight devices 67 0 k gmr 67 0 ai05667 (first matching entry)
43/150 m7020r timing diagrams for x68 using up to eight m7020r devices figure 24. 68-bit search for device 0 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) ale_l ai05668 a b a b a b a b dq d1 d2 d3 a1 a3 d4 (lhi[6:0]) (1) search3 (this device is the global winner.) search4 (miss on this device.) search1 (this device is the global winner.) search2 (miss on this device.) cfg = 00000000, hlat = 010, tlsz = 01, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 z z z z z 0 0 z z 1 1 z z 0 0 z z 1 1 1 z 1 z z z zz
m7020r 44/150 figure 25. 68-bit search for device 1 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) ale_l ai05669 a b a b a b a b dq d1 d2 d3 a2 d4 (lhi[6:0]) (1) search3 (local winner but not global winner.) search4 (miss on this device.) search1 (miss on this device.) search2 (this device is global winner.) cfg = 00000000, hlat = 010, tlsz = 01, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z z z z z 0 z 1 z 0 z 1 1 z z z
45/150 m7020r figure 26. 68-bit search for device 7 (last device) note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) ale_l ai05670 a b a b a b a b dq d1 d2 d3 a2 d4 (lhi[6:0]) (1) search3 (local winner but not global winner.) search4 (global winner.) search1 (miss on this device.) search2 (miss on this device.) cfg = 00000000, hlat = 010, tlsz = 01, lram = 1, ldev = 1 search1 search2 search3 search4 01 01 01 01 0 0 z 0 1 0 z 0 0 0 z 1 z 1 z z 1 0 0
m7020r 46/150 table 28. latency of search from instruction to sram access cycle, 68-bit, up to 8 devices table 29. shift of ssf and ssv from sadr 68-bit search on tables configured as x68 using up to 31 m7020r devices the hardware diagram of the search subsystem of 31 devices is shown in figure 27, page 48. each of the four blocks in the diagram represents eight m7020r devices (except the last, which has seven devices). the diagram for a block of eight devices is shown in figure 28, page 49. the following are the parameters programmed into the 31 devices: C first thirty devices (devices 0C29): cfg = 00000000, tlsz = 10, hlat = 001, lram = 0, and ldev = 0. C thirty-first device (device 30): cfg = 00000000, tlsz = 10, hlat = 001, lram = 1, and ldev = 1. note: all 31 devices must be programmed with the same values for tlsz and hlat. only the last de- vice in the table must be programmed with lram = 1 and ldev = 1 (device 30 in this case). all other upstream devices must be programmed with lram = 0 and ldev = 0 (devices 0 through 29 in this case). the timing diagrams referred to in this paragraph reference the hit/miss assumptions defined in table 30, page 47. for the purpose of illustrating the timings, it is further assumed that there is only one device with a matching entry in each of the blocks. figure 30, page 51 shows the timing dia- gram for a search command in the 68-bit-con- figured table of 31 devices for each of the eight devices in block number 0. figure 31, page 52 shows a timing diagram for a search command in the 68-bit-configured table of 31 devices for the all the devices in block number 1 (above the win- ning device in that block). figure 32, page 53 shows the timing diagram for the globally winning device (defined as the final winner within its own and all blocks) in block number 1. figure 33, page 54 shows the timing diagram for all the devices be- low the globally winning device in block number 1. figure 34, page 55, figure 35, page 56, and fig- ure 36, page 57 show the timing diagrams of the devices above the globally winning device, the glo- bally winning device, and the devices below the globally winning device, respectively, for block number 2. figure 37, page 58, figure 38, page 59, figure 39, page 60, and figure 40, page 61 show the timing diagrams of the devices above globally winning device, the globally winning device, and the devices below the globally winning device ex- cept the last device (device 30), respectively, for block number 3. # of devices max table size latency in clk cycles 1 (tlsz = 00) 32k x 68-bit 4 2C8 (tlsz = 01) 256k x 68-bit 5 9C31 (tlsz = 10) 992k x 68-bit 6 hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
47/150 m7020r the following is the sequence of operation for a single 68-bit search command (also refer to command codes, page 29). C cycle a: the host asic drives the cmdv high and applies search command code ('10') on cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair for use in this search operation. cmd[8:7] signals must be driven with the same bits that will be driven on sadr[21:20] by this device if it has a hit. dq[67:0] must be driven with the 68-bit data to be compared. the cmd[2] signal must be driv- en to a logic '0.' C cycle b: the host asic continues to drive the cmdv high and applies search command ('10') on cmd[1:0]. cmd[5:2] must be driven by the index of the comparand register pair for stor- ing the 136-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching en- try and the hit flag (see search-successful registers (ssr[0:7]), page 23). the dq[67:0] continues to carry the 68-bit data to be com- pared. note: for 68-bit searches, the host asic must supply the same 68-bit data on dq[67:0] during both cycles a and b. the even and odd pair of gmrs selected for the comparison must be pro- grammed with the same value. the logical 68-bit search operation is shown in figure 29, page 50. the entire table (31 devices of 68-bit entries) is compared to a 68-bit word k (pre- sented on the dq bus in both cycles a and b of the command) using the gmr and the local mask bits. the effective gmr is the 68-bit word speci- fied by the identical value in both even and odd gmr pairs in each of the eight devices and select- ed by the gmr index in the commands cycle a. the 68-bit word k (presented on the dq bus in both cycles a and b of the command) is also stored in both even and odd comparand register pairs in each of the eight devices and selected by the comparand register index in commands cy- cle b. in the x68 configuration, the even com- parand register can be subsequently used by the learn command only in the first non-full device. the word k (presented on the dq bus in both cy- cles a and b of the command) is compared with each entry in the table starting at location 0. the first matching entrys location address, l, is the winning address that is driven as part of the sram address on the sadr[21:0] lines (see sram ad- dressing, page 126). the global winning device will drive the bus in a specific cycle. on global miss cycles the device with lram = 1 and ldev = 1 will be the default driver for such missed cycles. the search command is a pipelined operation and executes a search at half the rate of the fre- quency of clk2x for 68-bit searches in x68-con- figured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 68-bit search command cycle (two clk2x cycles) is shown in table 31, page 62. for up to 31 devices in the table (tlsz = 10), search latency from command to sram access cycle is 6. in addition, ssv and ssf shift further to the right for different values of hlat, as specified in table 32, page 62. the 68-bit search operation is pipelined and ex- ecutes as follows: C four cycles from the search comm and, each of the devices knows the outcome internal to it for that operation; C in the fifth cycle after the search command, the devices in a block arbitrate for a winner amongst them (a block being defined as less than or equal to eight devices resolving the win- ner within them using the lhi[6:0] and lho[1:0] signalling mechanism); C in the sixth cycle after the search comm and, the blocks (of devices) resolve the winning block through the bhi[2:0] and bho[2:0] signalling mechanism. the winning device within the win- ning block is the global winning device for a search operation. table 30. hit/miss assumption search number1234 block 0 miss miss miss miss block 1 miss miss hit miss block 2 miss hit hit miss block 3 hit hit miss miss
m7020r 48/150 figure 27. hardware diagram for a table with 31 devices sram bhi[2] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] block of 8 m7020rs, block 0 (devices 0-7) block of 8 m7020rs, block 1 (devices 8-15) block of 8 m7020rs, block 2 (devices 16-23) block of 7 m7020rs, block 3 (devices 24-30) ai05671 gnd gnd gnd ssf, ssv cmd[8:0], cmdv dq[67:0]
49/150 m7020r figure 28. hardware diagram for a block of up to eight devices dq[67:0] sram bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bho[2] bho[1] bho[0] bho[2] bho[1] bho[0] lho[1] lho[0] lho[0] lho[1] lho[0] lho[0] lho[0] lho[0] lho[0] lho[1] lho[1] lho[1] lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi 3210 3210 3210 3210 3210 3210 3210 3210 m7020r #0 m7020r #1 m7020r #2 m7020r #3 m7020r #4 m7020r #5 m7020r #6 m7020r #7 lho[0] 654 654 654 654 654 654 654 654 ai05672 cmdv cmd[8:0] ssv, ssf
m7020r 50/150 figure 29. x68 table with 31 devices comparand register (even) comparand register (odd) 67 0 k cfg = 00000000 0 1 2 3 1015807 (68-bit configuration) location address l k must be the same for each of the 31 devices will be the same in each of the 31 devices 67 0 k gmr 67 0 ai05673 (first matching entry)
51/150 m7020r timing diagrams for x68 using up to 31 m7020r devices figure 30. each device in block number 0 (miss on each device) note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) ale_l ai05674 a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) bho[2:0] (4) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 00000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z 0 0 0 0 z z z z z z
m7020r 52/150 figure 31. each device above the winning device in block number 1 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) ale_l ai05674 a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) bho[2:0] (4) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 00000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z 0 0 0 0 z z z z z z
53/150 m7020r figure 32. globally winning device in block number 1 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai05675 a b a b a b a b dq d1 d2 d3 a3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (this device global winner.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 00000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 0 z z z z z z z z z z z
m7020r 54/150 figure 33. devices below the winning device in block number 1 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai05676 a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 00000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 0 z z z z z
55/150 m7020r figure 34. devices above the winning device in block number 2 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai05677 a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 00000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 0 z z z z z
m7020r 56/150 figure 35. globally winning device in block number 2 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai05678 a b a b a b a b dq d1 d2 d3 a2 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (hit but not a winner.) search4 (miss on this device.) search1 (miss on this device.) search2 (global winner.) cfg = 00000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 1 1 1 0 0 0 z z z z z z z z z z z
57/150 m7020r figure 36. devices below the winning device in block number 2 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai05679 a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 00000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 0 z z z z z
m7020r 58/150 figure 37. devices above the winning device in block number 3 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai05680 a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 00000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 0 z z z z z
59/150 m7020r figure 38. globally winning device in block number 3 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai05681 a b a b a b a b dq d1 d2 d3 a1 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (global winner.) search2 (hit but not a global winner.) cfg = 00000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 1 1 1 0 0 0 z z z z z z z z z z z
m7020r 60/150 figure 39. devices below the winning device in block number 3 (not device 30 - last device) note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai05682 a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 00000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 0 z z z z z
61/150 m7020r figure 40. device 6 in block number 3 (device 30 in depth-cascaded table) note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai05683 a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (hit on some device above.) search4 (global miss; this device default driver.) search1 (hit on some device above.) search2 (hit on some device above.) cfg = 00000000, hlat = 001, tlsz = 10, lram = 1, ldev = 1 search1 search2 search3 search4 01 01 01 01 0 0 z z z z z 0 0 0 0 z 0 1 0 0 0 1 1 0 0
m7020r 62/150 table 31. latency of search from instruction to sram access cycle, 68-bit, up to 31 devices table 32. shift of ssf and ssv from sadr 136-bit configuration with single device the hardware diagram for this search subsystem is shown in figure 41. figure 42, page 64 shows the timing diagram for a search command in the 136-bit-configured ta- ble (cfg = 01010101) consisting of a single de- vice for one set of parameters. this illustration assumes that the host asic has programmed tlsz to '00,' hlat to '001,' lram to '1,' and ldev to '1.' the following is the operation sequence for a sin- gle 136-bit search command (refer to com- mand codes and parameters, page 29). C cycle a: the host asic drives the cmdv high and applies search command code ('10') to cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair for use in this search operation. cmd[8:7] signals must be driven with the same bits that will be driven on sadr[21:20] by this device if it has a hit. dq[67:0] must be driven with the 68-bit data ([135:68]) to be compared against all even loca- tions. the cmd[2] signal must be driven to logic '0.' C cycle b: the host asic continues to drive the cmdv high and applies the command code of search command ('10') on cmd[1:0]. cmd[5:2] must be driven by the index of the comparand register pair for storing the 136-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and hit flag (see search-successful registers (ssr[0:7]), page 23). the dq[67:0] is driven with 68-bit data ([67:0]), compared to all odd locations. note: for 136-bit searches, the host asic must supply two distinct 68-bit data words on dq[67:0] during cycles a and b. the even- numbered gmr of the pair specified by the gmr index is used for masking the word in cy- cle a. the odd-numbered gmr of the pair spec- ified by the gmr index is used for masking the word in cycle b. # of devices max table size latency in clk cycles 1 (tlsz = 00) 32k x 68-bit 4 2C8 (tlsz = 01) 256k x 68-bit 5 9C31 (tlsz = 10) 992k x 68-bit 6 hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
63/150 m7020r the logical 136-bit search operation is shown in figure 43, page 65. the entire table of 136-bit en- tries is compared to a 136-bit word k (presented on the dq bus in cycles a and b of the command) using the gmr and the local mask bits. the gmr is the 136-bit word specified by the even and odd global mask pair selected by the gmr index in the commands cycle a. the 136-bit word k (present- ed on the dq bus in cycles a and b of the com- mand) is also stored in both even and odd comparand register pairs selected by the com- parand register index in the commands cycle b. the two comparand registers can subsequently be used by the learn command with the even comparand register stored in an even location, and the odd comparand register stored in an adja- cent odd location. the word k (presented on the dq bus in cycles a and b of the command) is compared with each entry in the table starting at location 0. the first matching entrys location ad- dress, l, is the winning address that is driven as part of the sram address on the sadr[21:0] lines (see sram addressing, page 126). note: the matching address is always going to an even address for a 136-bit search. the search command is a pipelined operation that executes searches at half the rate of the fre- quency of clk2x for 136-bit searches in x136- configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 136-bit search command cycle (two clk2x cycles) is shown in table 33, page 65. for a single device in the table with tlsz = 00, the latency of the search from command to sram access cycle is 4. in addition, ssv and ssf shift further to the right for different values of hlat, as specified in table 34, page 65. figure 41. hardware diagram for a table with 1 device dq[67:0] cmdv, cmd[8:0] ssf, ssv sram bhi[2:0] bho[2:0] lho[1] lhi 3210 m7020r lho[0] 654 ai06329
m7020r 64/150 figure 42. timing diagram for a 136-bit search for one device cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l ale_l ai06330 a b a b a b a b a b a b a b a b dq d1 d2 d3 a1 a3 d4 search3 hit search4 miss search1 hit search2 miss cfg = 01010101, hlat = 001, tlsz = 00, lram = 1, ldev = 1 search1 search2 search3 search4 01 01 01 01 1 1 1 1 1 0 0 0 1 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0
65/150 m7020r figure 43. x136 table with one device table 33. latency of search from instruction to sram access cycle, 136-bit, 1 device table 34. shift of ssf and ssv from sadr # of devices max table size latency in clk cycles 1 (tlsz = 00) 16k x 136-bit 4 2C8 (tlsz = 01) 128k x 136-bit 5 9C31 (tlsz = 10) 496k x 136-bit 6 hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 comparand register (even) comparand register (odd) 67 0 a cfg = 01010101 0 2 4 6 32766 (136-bit configuration) location address l b 135 0 k gmr 135 0 ai06331 (first matching entry) even odd b a
m7020r 66/150 136-bit search on tables configured as x136 using up to eight m7020r devices the hardware diagram of the search subsystem of eight devices is shown in figure 44, page 67. the following are parameters programmed into the eight devices: C first seven devices (devices 0C6): cfg = 01010101, tlsz = 01, hlat = 010, lram = 0, and ldev = 0. C eighth device (device 7): cfg = 01010101, tlsz = 01, hlat = 010, lram = 1, and ldev = 1. note: all eight devices must be programmed with the same value of tlsz and hlat. only the last device in the table must be programmed with lram = 1 and ldev = 1 (device 7 in this case). all other upstream devices must be programmed with lram = 0 and ldev = 0 (devices 0 through 6 in this case). figure 46, page 69 shows the timing diagram for a search command in the 136-bit-configured ta- ble of eight devices for device 0. figure 47, page 70 shows the timing diagram for a search com- mand in the 136-bit-configured table consisting of eight devices for device 1. figure 48, page 71 shows the timing diagram for a search com- mand in the 136-bit configured table consisting of eight devices for device 7 (the last device in this specific table). for these timing diagrams, four 136-bit searches are performed sequentially, and the following hit/miss assumptions were made (see table 35) the following is the sequence of operation for a single 136-bit search command (see com- mand codes and parameters, page 29). C cycle a: the host asic drives cmdv high and applies search command code ('10') on cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair for use in this search operation. cmd[8:7] signals must be driven with the same bits that will be driven by this device on sadr[21:20] if it has a hit. dq[67:0] must be driven with the 68-bit data ([135:68]) in order to be compared against all even locations. the cmd[2] signal must be driv- en to a logic '0.' C cycle b: the host asic continues to drive cmdv high and to apply the command code for search command ('10') on cmd[1:0]. cmd[5:2] must be driven by the index of the comparand register pair for storing the 136-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the ssr index that will be used for storing the address of the matching entry and the hit flag (see search-successful registers (ssr[0:7]), page 23). the dq[67:0] is driven with 68-bit data ([67:0]) compared against all odd locations. the logical 136-bit search operation is shown in figure 45, page 68. the entire table (eight devices of 136-bit entries) is compared to a 136-bit word k (presented on the dq bus in cycles a and b of the command) using the gmr and local mask bits. the gmr is the 136-bit word specified by the even and odd global mask pair selected by the gmr in- dex in the commands cycle a. the 136-bit word k (presented on the dq bus in cycles a and b of the command) is also stored in the even and odd comparand registers specified by the comparand register index in the com- mands cycle b. in x136 configurations, the even and odd comparand registers can subsequently be used by the learn command in only one of the devices (the first non-full device). the word k (presented on the dq bus in cycles a and b of the command) is compared to each entry in the table starting at location 0. the first matching entrys location, l, is the winning address that is driven as part of the sram address on the sadr[21:0] lines (see sram addressing, page 126). the global winning device will drive the bus in a specif- ic cycle. on global miss cycles the device with lram = 1 (the default driving device for the sram bus) and ldev = 1 (the default driving device for ssf and ssv signals) will be the default driver for such missed cycles. note: during 136-bit searches of 136-bit-config- ured tables, the search hit will always be at an even address. the search command is a pipelined operation and executes a search at half the rate of the fre- quency of clk2x for 136-bit searches in x136- configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 136-bit search command cycle (two clk2x cycles) is shown in table 36, page 72. for one to eight devices in the table and tlsz = 01, the latency of a search from com- mand to sram access cycle is 5. in addition, ssv and ssf shift further to the right for different val- ues of hlat as specified in table 37, page 72.
67/150 m7020r table 35. hit/miss assumption figure 44. hardware diagram for a table with eight devices search number1234 device 0 hit miss hit miss device 1 miss hit hit miss device 2-6 miss miss miss miss device 7 miss miss hit hit sram bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bho[2] bho[1] bho[0] bho[2] bho[1] bho[0] lho[1] lho[0] lho[0] lho[1] lho[0] lho[0] lho[0] lho[0] lho[0] lho[1] lho[1] lho[1] lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi 3210 3210 3210 3210 3210 3210 3210 3210 m7020r #0 m7020r #1 m7020r #2 m7020r #3 m7020r #4 m7020r #5 m7020r #6 m7020r #7 lho[0] 654 654 654 654 654 654 654 654 ai05666 ssf, ssv dq[67:0] cmdv cmd[8:0]
m7020r 68/150 figure 45. x136 table with eight devices comparand register (even) comparand register (odd) 67 0 a cfg = 01010101 0 2 4 6 262142 (136-bit configuration) location address l b 135 0 k gmr 135 0 ai06332 (first matching entry) even odd b a must be the same in each of the eight devices will be the same in each of the eight devices
69/150 m7020r timing diagrams for x136 using up to eight m7020r devices figure 46. 136-bit search for device number 0 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) ale_l ai06333 a b a b a b a b a b a b a b a b dq d1 d2 d3 a1 a3 d4 (lhi[6:0]) (1) search3 (this device is the global winner.) search4 (miss on this device.) search1 (this device is the global winner.) search2 (miss on this device.) cfg = 01010101, hlat = 010, tlsz = 01, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 z z z z z 0 0 z z 1 1 z z 0 0 z z 1 1 1 z 1 z z z zz
m7020r 70/150 figure 47. 136-bit search for device number 1 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) ale_l ai06334 a b a b a b a b a b a b a b a b dq d1 d2 d3 a2 d4 (lhi[6:0]) (1) search3 (local winner but not global winner.) search4 (miss on this device.) search1 (miss on this device.) search2 (this device is global winner.) cfg = 01010101, hlat = 010, tlsz = 01, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z z z z z 0 z 1 z 0 z 1 1 z z z
71/150 m7020r figure 48. 136-bit search for device number 7 (last device) note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) ale_l ai06335 a b a b a b a b a b a b a b a b dq d1 d2 d3 a4 d4 (lhi[6:0]) (1) search3 (local winner but not global winner.) search4 (global winner.) search1 (miss on this device.) search2 (miss on this device.) cfg = 01010101, hlat = 010, tlsz = 01, lram = 1, ldev = 1 search1 search2 search3 search4 01 01 01 01 0 0 z 0 1 0 z 0 0 0 z 1 z 1 z z 1 0 0
m7020r 72/150 table 36. latency of search from instruction to sram access cycle, 136-bit, up to 8 devices table 37. shift of ssf and ssv from sadr 136-bit search on tables configured as x136 using up to 31 m7020r devices the hardware diagram of the search subsystem of 31 devices is shown in figure 49, page 74. each of the four blocks in the diagram represents a block of eight m7020r devices (except the last, which has seven devices).the diagram for a block of eight devices is shown in figure 50, page 75. following are the parameters programmed into the 31 devices. first thirty devices (devices 0C29): cfg = 01010101, tlsz = 10, hlat = 001, lram = 0, and ldev = 0. thirty-first device (device 30): cfg = 01010101, tlsz = 10, hlat = 001, lram = 1, and ldev = 1. note: all 31 devices must be programmed with the same value of tlsz and hlat. only the last de- vice in the table must be programmed with lram = 1 and ldev = 1 (device 30 in this case). all other upstream devices must be programmed with lram = 0 and ldev = 0 (devices 0 through 29 in this case). the timing diagrams referred to in this paragraph reference the hit/miss assumptions defined in table 38, page 73. for the purpose of illustrating timings, it is further assumed that the there is only one device with a matching entry in each of the blocks. figure 52, page 77 shows the timing dia- gram for a search command in the 136-bit-con- figured table (31 devices) for each of the eight devices in block 0. figure 53, page 78 shows the timing diagram for search command in the 68-bit-configured table (31 devices) for all the de- vices in block 1 above the winning device in that block. figure 54, page 79 shows the timing dia- gram for the globally winning device (the final win- ner within its own block and all blocks) in block 1. figure 55, page 80 shows the timing diagram for all the devices below the globally winning device in block 1. figure 56, page 81, figure 57, page 82, and figure 58, page 83 respectively show the tim- ing diagrams of the devices above globally win- ning device, the globally winning device and devices below the globally winning device for block 2. figure 59, page 84, figure 60, page 85, figure 61, page 86, and figure 62, page 87 re- spectively show the timing diagrams of the devices above the globally winning device, the globally winning device, and devices below the globally winning device except the last device (device 30), and the last device (device 30) for block 3. # of devices max table size latency in clk cycles 1 (tlsz = 00) 16k x 136-bit 4 2C8 (tlsz = 01) 128k x 136-bit 5 9C31 (tlsz = 10) 496k x 136-bit 6 hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
73/150 m7020r the following is the sequence of operation for a single 136-bit search command (see com- mand codes and parameters, page 29). C cycle a: the host asic drives the cmdv high and applies search command code ('10') on cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair for use in this search operation. cmd[8:7] signals must be driven with the bits that will be driven on sadr[21:20] by this device if it has a hit. dq[67:0] must be driven with the 68-bit data ([135:68]) in order to be compared against all even locations. the cmd[2] signal must be driv- en to logic '0.' C cycle b: the host asic continues to drive the cmdv high and to apply search command code ('10') on cmd[1:0]. cmd[5:2] must be driv- en by the index of the comparand register pair for storing the 136-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and the hit flag (see search- successful registers (ssr[0:7]), page 23). the dq[67:0] is driven with 68-bit data ([67:0]) to be compared against all odd locations. the logical 136-bit search operation is as shown in figure 51, page 76. the entire table of 31 devices (consisting of 136-bit entries) is compared against a 136-bit word k that is presented on the dq bus in cycles a and b of the command using the gmr and local mask bits. the gmr is the 136- bit word specified by the even and odd global mask pair selected by the gmr index in the com- mands cycle a. the 136-bit word k that is presented on the dq bus in cycles a and b of the command is also stored in the even and odd comparand registers specified by the comparand register index in the commands cycle b. in x136 configurations, the even and odd comparand registers can subse- quently be used by the learn command in only the first non-full device. note: the learn command is supported for only one of the blocks consisting of up to eight devices in a depth-cascaded table of more than one block. the word k that is presented on the dq bus in cy- cles a and b of the command is compared with each entry in the table starting at location 0. the first matching entrys location address, l, is the winning address that is driven as part of the sram address on the sadr[21:0] lines (see sram ad- dressing, page 126). the global winning device will drive the bus in a specific cycle. on global miss cycles the device with lram = 1 (the default driv- ing device for the sram bus) and ldev = 1 (the default driving device for ssf and ssv signals) will be the default driver for such missed cycles. note: during 136-bit searches of 136-bit-config- ured tables, the search hit will always be at an even address. the search command is a pipelined operation. it executes a search at half the rate of the frequen- cy of clk2x for 136-bit searches in x136-config- ured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 136-bit search command cycle (two clk2x cycles) is shown in table 39, page 88. the latency of a search from command to the sram access cycle is 6 for 1C31 devices in the ta- ble and where tlsz = 10. in addition, ssv and ssf shift further to the right for different values of hlat, as specified in table 40, page 88. the 136-bit search operation is pipelined and executes as follows: C four cycles from the search comm and, each of the devices knows the outcome internal to it for that operation. C in the fifth cycle after the search command, the devices in a block (being less than or equal to eight devices resolving the winner within them using the lhi[6:0] and lho[1:0] signalling mechanism) arbitrate for a winner amongst them. C in the sixth cycle after the search comm and, the blocks (of devices) resolve the winning block through the bhi[2:0] and bho[2:0] signalling mechanism. the winning device in the winning block is the global winning device for a search operation. table 38. hit/miss assumption search number1234 block 0 miss miss miss miss block 1 miss miss hit miss block 2 miss hit hit miss block 3 hit hit miss miss
m7020r 74/150 figure 49. hardware diagram for a table with 31 devices sram bhi[2] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] block of 8 m7020rs, block 0 (devices 0-7) block of 8 m7020rs, block 1 (devices 8-15) block of 8 m7020rs, block 2 (devices 16-23) block of 7 m7020rs, block 3 (devices 24-30) ai05671 gnd gnd gnd ssf, ssv cmd[8:0], cmdv dq[67:0]
75/150 m7020r figure 50. hardware diagram for a block of up to eight devices dq[67:0] sram bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bho[2] bho[1] bho[0] bho[2] bho[1] bho[0] lho[1] lho[0] lho[0] lho[1] lho[0] lho[0] lho[0] lho[0] lho[0] lho[1] lho[1] lho[1] lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi 3210 3210 3210 3210 3210 3210 3210 3210 m7020r #0 m7020r #1 m7020r #2 m7020r #3 m7020r #4 m7020r #5 m7020r #6 m7020r #7 lho[0] 654 654 654 654 654 654 654 654 ai05672 cmdv cmd[8:0] ssv, ssf
m7020r 76/150 figure 51. x136 table with 31 devices comparand register (even) comparand register (odd) 67 0 a cfg = 01010101 0 2 4 6 1015806 (136-bit configuration) location address l b 135 0 k gmr 135 0 ai05684 (first matching entry) even odd b a must be the same in each of the 31 devices will be the same in each of the 31 devices
77/150 m7020r timing diagrams for x136 using up to 31 m7020r devices figure 52. each device in block number 0 (miss on each device) note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) ale_l ai05685 a b a b a b a b a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) bho[2:0] (4) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 01010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z 0 0 0 0 z z z z z z
m7020r 78/150 figure 53. each device above the winning device in block number 1 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) ale_l ai05685 a b a b a b a b a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) bho[2:0] (4) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 01010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z 0 0 0 0 z z z z z z
79/150 m7020r figure 54. globally winning device in block number 1 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai05686 a b a b a b a b a b a b a b a b dq d1 d2 d3 a3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (this device global winner.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 01010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 1 1 1 0 0 0 z z z z z z z z z z z
m7020r 80/150 figure 55. devices below the winning device in block number 1 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai05687 a b a b a b a b a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 01010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 0 z z z z z
81/150 m7020r figure 56. devices above the winning device in block number 2 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai05688 a b a b a b a b a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 01010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 0 z z z z z
m7020r 82/150 figure 57. globally winning device in block number 2 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai05689 a b a b a b a b a b a b a b a b dq d1 d2 d3 a2 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (hit but not a winner.) search4 (miss on this device.) search1 (miss on this device.) search2 (global winner.) cfg = 01010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 1 1 1 0 0 0 z z z z z z z z z z z
83/150 m7020r figure 58. devices below the winning device in block number 2 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai05690 a b a b a b a b a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 01010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 0 z z z z z
m7020r 84/150 figure 59. devices above the winning device in block number 3 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai05691 a b a b a b a b a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 01010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 0 z z z z z
85/150 m7020r figure 60. globally winning device in block number 3 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai05692 a b a b a b a b a b a b a b a b dq d1 d2 d3 a1 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (global winner.) search2 (hit but not a global winner.) cfg = 01010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 1 1 1 0 0 0 z z z z z z z z z z z
m7020r 86/150 figure 61. devices below the winning device in block number 3 (not device 30 - last device) note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai05693 a b a b a b a b a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 01010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 0 z z z z z
87/150 m7020r figure 62. device 6 in block number 3 (device 30 in depth-cascaded table) note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai05694 a b a b a b a b a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (hit on some device above.) search4 (global miss; this device default driver.) search1 (hit on some device above.) search2 (hit on some device above.) cfg = 01010101, hlat = 001, tlsz = 10, lram = 1, ldev = 1 search1 search2 search3 search4 01 01 01 01 0 0 z z z z z 0 0 0 0 z 0 1 0 0 0 1 1 0 0
m7020r 88/150 table 39. latency of search from instruction to sram access cycle, 136-bit, up to 31 devices table 40. shift of ssf and ssv from sadr 272-bit search on tables configured as x272 using a single m7020r device the hardware diagram for this search subsystem is shown in figure 63, page 89. figure 64, page 90 shows the timing diagram for a search com- mand in the 272-bit-configured table (cfg = 10101010) consisting of a single device for one set of parameters: tlsz = '00,' hlat = '001,' lram = '1,' and ldev = '1.' the following is the sequence of operation for a single 136-bit search command (also refer to command codes and parameters, page 29). C cycle a: the host asic drives the cmdv high and applies search command code ('10') on cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair used for bits [271:136] of the data being searched. dq[67:0] must be driven with the 68-bit data ([271:204]) to be compared to all locations 0 in the four 68-bits-word page. the cmd[2] signal must be driven to logic 1. note: cmd[2] = 1 signals that the search is a x272-bit search. cmd[8:3] in this cycle is ig- nored. C cycle b: the host asic continues to drive the cmdv high and continues to apply the com- mand code of search command ('10') on cmd[1:0]. the dq[67:0] is driven with the 68-bit data ([204:136]) to be compared to all locations 1 in the four 68-bits-word page. C cycle c: the host asic drives the cmdv high and applies search command code ('10') on cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair used for bits [135:0] of the data being searched. cmd[8:7] signals must be driven with the bits that will be driven on sadr[21:20] by this de- vice if it has a hit. dq[67:0] must be driven with the 68-bit data ([135:68]) to be compared to all locations 2 in the four 68-bits-word page. the cmd[2] signal must be driven to logic '0.' C cycle d: the host asic continues to drive the cmdv high and applies search command code ('10') on cmd[1:0]. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching en- try and the hit flag (see search-successful registers (ssr[0:7]), page 23). the dq[67:0] is driven with the 68-bit data ([67:0]) to be com- pared to all locations 3 in the four 68-bits-word page. cmd[5:2] is ignored because the learn instruction is not supported for x272 tables. note: for 272-bit searches, the host asic must supply four distinct 68-bit data words on dq[67:0] during cycles a, b, c, and d. the gmr index in cycle a selects a pair of gmrs that apply to dq data in cycles a and b. the gmr index in cycle c selects a pair of gmrs that apply to dq data in cycles c and d. # of devices max table size latency in clk cycles 1 (tlsz = 00) 16k x 136-bit 4 2C8 (tlsz = 01) 128k x 136-bit 5 9C31 (tlsz = 10) 496k x 136-bit 6 hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
89/150 m7020r the logical 272-bit search operation is shown in figure 65, page 91. the entire table of 272-bit en- tries is compared to a 272-bit word k that is pre- sented on the dq bus in cycles a, b, c, and d of the command using the gmr and local mask bits. the gmr is the 272-bit word specified by the two pairs of gmrs selected by the gmr indexes in the commands cycles a and c. the 272-bit word k that is presented on the dq bus in cycles a, b, c, and d of the command is compared with each en- try in the table starting at location 0. the first matching entrys location address, l, is the win- ning address that is driven as part of the sram address on sadr[21:0] lines (see sram ad- dressing, page 126). note: the matching address is always going to be location 0 in a four-entry page for a 272-bit search (two lsbs of the matching index w ill be '00'). the search command is a pipelined operation and executes at one-fourth the rate of the frequen- cy of clk2x for 272-bit searches in x272-config- ured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 272-bit search command (measured in clk cycles) from the clk2x cycle that contains the c and d cycles is shown in table 41, page 91. the latency of a search from command to sram access cycle is 4 for only a single device in the table and tlsz = 00. in addition, ssv and ssf shift further to the right for different values of hlat, as specified in table 42, page 91. figure 63. hardware diagram for a table with one device dq[67:0] cmdv, cmd[8:0] ssf, ssv sram bhi[2:0] bho[2:0] lho[1] lhi 3210 m7020r lho[0] 654 ai05695
m7020r 90/150 figure 64. timing diagram for a 272-bit search for one device cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l ale_l ai05696 a b a b a b a b a b c d a b c d dq d1 d2 a1 search1 hit search2 miss cfg = 10101010, hlat = 001, tlsz = 00, lram = 1, ldev = 1 search1 search2 01 01 1 1 1 1 0 0 1 1 1 0 0 0 0 1 0 0 1 1 0 0
91/150 m7020r figure 65. x272 table with one device table 41. latency of search from cycles c and d to sram access cycle, 272-bit, 1 device table 42. shift of ssf and ssv from sadr # of devices max table size latency in clk cycles 1 (tlsz = 00) 8k x 272-bit 4 2C8 (tlsz = 01) 64k x 272-bit 5 9C31 (tlsz = 10) 248k x 272-bit 6 hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 cfg = 10101010 0 4 8 12 32764 (272-bit configuration) location address l 271 0 k gmr 271 0 ai05697 (first matching entry) 0 123 bcd a
m7020r 92/150 272-bit search on tables x272-configured using up to eight m7020r devices the hardware diagram of the search subsystem of eight devices is shown in figure 66, page 94. the following are the parameters programmed in the eight devices. C first seven devices (devices 0C6): cfg = 10101010, tlsz = 01, hlat = 000, lram = 0, and ldev = 0. C eighth device (device 7): cfg = 10101010, tlsz = 01, hlat = 000, lram = 1, and ldev = 1. note: all eight devices must be programmed with the same value of tlsz and hlat. only the last device in the table must be programmed with lram = 1 and ldev = 1 (device 7 in this case). all other upstream devices must be programmed with lram = 0 and ldev = 0 (devices 0 through 6 in this case). figure 68, page 96 shows the timing diagram for a search command in the 272-bit-configured ta- ble of eight devices for device 0. figure 69, page 97 shows the timing diagram for a search com- mand in the 272-bit-configured table of eight de- vices for device 1. figure 70, page 98 shows the timing diagram for a search command in the 272-bit-configured table of eight devices for de- vice 7 (the last device in this specific table). for these timing diagrams three 272-bit searches are performed sequentially. the following hit/miss assumptions were made as shown in table 43, page 93. the following is the sequence of operation for a single 272-bit search command (also com- mand codes and parameters, page 29). C cycle a: the host asic drives the cmdv high and applies search command code ('10') on cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair used for bits [271:136] of the data being searched in this operation. dq[67:0] must be driven with the 68- bit data ([271:204]) to be compared against all locations 0 in the four-word, 68-bit page. the cmd[2] signal must be driven to logic '1.' note: cmd[2] = 1 signals that the search is a 272-bit search. cmd[8:3] in this cycle is ig- nored. C cycle b: the host asic continues to drive the cmdv high and applies search command code ('10') on cmd[1:0]. the dq[67:0] is driven with the 68-bit data ([203:136]) to be compared against all locations 1 in the four 68-bits-word page. C cycle c: the host asic drives the cmdv high and applies search command code ('10') on cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair used for bits [135:0] of the data being searched. cmd[8:7] signals must be driven with the bits that will be driven on sadr[21:20] by this de- vice if it has a hit. dq[67:0] must be driven with the 68-bit data ([135:68]) to be compared against all locations 2 in the four 68-bits-word page. the cmd[2] signal must be driven to logic '0.' C cycle d: the host asic continues to drive the cmdv high and applies search command code ('10') on cmd[1:0]. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching en- try and the hit flag (see search-successful registers (ssr[0:7]), page 23). the dq[67:0] is driven with the 68-bit data ([67:0]) to be com- pared to all locations 3 in the four 68-bits-word page. cmd[5:2] is ignored because the learn instruction is not supported for x272 tables. note: for 272-bit searches, the host asic must supply four distinct 68-bit data words on dq[67:0] during cycles a, b, c, and d. the gmr index in cycle a selects a pair of gmrs in each of the eight devices that apply to dq data in cycles a and b. the gmr index in cycle c selects a pair of gmrs in each of the eight de- vices that apply to dq data in cycles c and d. the logical 272-bit search operation is shown in figure 67, page 95. the entire table of 272-bit en- tries is compared to a 272-bit word k that is pre- sented on the dq bus in cycles a, b, c, and d of the command using the gmr and the local mask bits. the gmr is the 272-bit word specified by the two pairs of gmrs selected by the gmr indexes in the commands cycles a and c in each of the eight devices. the 272-bit word k that is presented on the dq bus in cycles a, b, c, and d of the com- mand is compared to each entry in the table start- ing at location 0. the first matching entrys location address, l, is the winning address that is driven as part of the sram address on the sadr[23:0] lines (see sram addressing, page 126). note: the matching address is always going to be a location 0 in a four-entry page for 272-bit search (two lsbs of the matching index w ill be '00').
93/150 m7020r the search command is a pipelined operation and executes search at one-fourth the rate of the frequency of clk2x for 272-bit searches in x272- configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 272-bit search command (measured in clk cycles) from the clk2x cycle that contains the c and d cycles is shown in table 44, page 99. the latency of search from command to sram ac- cess cycle is 5 for only a single device in the table and tlsz = 01. in addition, ssv and ssf shift fur- ther to the right for different values of hlat, as specified in table 45, page 99. table 43. hit/miss assumption search number 1 2 3 device 0 hit miss miss device 1 miss hit miss device 2-6 miss miss miss device 7 miss miss miss
m7020r 94/150 figure 66. hardware diagram for a table with eight devices sram bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bho[2] bho[1] bho[0] bho[2] bho[1] bho[0] lho[1] lho[0] lho[0] lho[1] lho[0] lho[0] lho[0] lho[0] lho[0] lho[1] lho[1] lho[1] lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi 3210 3210 3210 3210 3210 3210 3210 3210 m7020r #0 m7020r #1 m7020r #2 m7020r #3 m7020r #4 m7020r #5 m7020r #6 m7020r #7 lho[0] 654 654 654 654 654 654 654 654 ai05666 ssf, ssv dq[67:0] cmdv cmd[8:0]
95/150 m7020r figure 67. x272 table with eight devices cfg = 10101010 0 4 8 12 262140 (272-bit configuration) location address l 271 0 k gmr 271 0 ai05698 (first matching entry) 0 123 bcd a must be the same in each of eight devices
m7020r 96/150 timing diagrams for x272-configured using up to eight m7020r devices figure 68. 272-bit search for device number 0 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) ale_l ai05699 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 a1 (lhi[6:0]) (1) search3 (miss on this device.) search1 (this device is the global winner.) search2 (miss on this device.) cfg = 10101010, hlat = 000, tlsz = 01, lram = 0, ldev = 0 search1 search2 search3 01 01 01 z z 0 z z z z 0 z 1 z 0 z 1 1 z z z z z
97/150 m7020r figure 69. 272-bit search for device number 1 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) ale_l ai06300 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 a2 (lhi[6:0]) (1) search3 (miss on this device.) search1 (miss on this device.) search2 (this device is global winner.) cfg = 10101010, hlat = 000, tlsz = 01, lram = 0, ldev = 0 search1 search2 search3 01 01 01 z z z z z 0 z 1 z 0 z 1 1 z z z z
m7020r 98/150 figure 70. 272-bit search for device number 7 (last device) note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) ale_l ai06301 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 a2 (lhi[6:0]) (1) search3 (global miss.) search1 (miss on this device.) search2 (miss on this device.) cfg = 10101010, hlat = 000, tlsz = 01, lram = 1, ldev = 1 search1 search2 search3 01 01 01 0 0 1 0 0 z z z 0 0 0 z z 0 0 z z 1 1 z z z 0 0
99/150 m7020r table 44. latency of search from cycles c and d to sram access cycle, 272-bit, up to 8 devices table 45. shift of ssf and ssv from sadr 272-bit search on tables configured as x272 using up to 31 m7020r devices the hardware diagram of the search subsystem of 31 devices is shown in figure 71, page 101. each of the four blocks in the diagram represents a block of eight m7020r devices, except the last which has seven devices.the diagram for a block of eight devices is shown in figure 72, page 102. the following are the parameters programmed into the 31 devices. C first thirty devices (devices 0C29): cfg = 10101010, tlsz = 10, hlat = 000, lram = 0, and ldev = 0. C thirty-first device (device 30): cfg = 10101010, tlsz = 10, hlat = 000, lram = 1, and ldev = 1. note: all 31 devices must be programmed with the same value of tlsz and hlat. only the last de- vice in the table must be programmed with lram = 1 and ldev = 1 (device 30 in this case). all other upstream devices must be programmed with lram = 0 and ldev = 0 (devices 0 through 29 in this case). the timing diagrams referred to in this paragraph reference the hit/miss assumptions defined in table 46, page 101. for the purpose of illustrating the timings, it is further assumed that there is only one device with the matching entry in each block. figure 74, page 104 shows the timing diagram for a search command in the 272-bit-configured ta- ble consisting of 31 devices for each of the eight devices in block 0. figure 75, page 105 shows the timing diagram for a search command in the 272-bit-configured table of 31 devices for all devic- es above the winning device in block 1. figure 76, page 106 shows the timing diagram for the global- ly winning device (the final winner within its own and all blocks) in block 1. figure 77, page 107 shows the timing diagram for all the devices below the globally winning device in block 1. figure 78, page 108, figure 79, page 109, and figure 80, page 110, respectively, show the timing diagrams of the devices above the globally winning device, the globally winning device, and the devices below the globally winning device for block 2. figure 81, page 111, figure 82, page 112, figure 83, page 113, and figure 84, page 114, respectively, show the timing diagrams of the device above the glo- bally winning device, the globally winning device, the devices below the globally winning device (ex- cept device 30), and last device (device 30) for block 3. # of devices max table size latency in clk cycles 1 (tlsz = 00) 8k x 272-bit 4 2C8 (tlsz = 01) 64k x 272-bit 5 9C31 (tlsz = 10) 248k x 272-bit 6 hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
m7020r 100/150 the following is the sequence of operation for a single 272-bit search command (see com- mand codes and parameters, page 29). C cycle a: the host asic drives the cmdv high and applies search command code ('10') on cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair used for bits [271:136] of the data being searched. dq[67:0] must be driven with the 68-bit data ([271:204])to be compared to all locations 0 in the four 68-bit-word page. the cmd[2] signal must be driven to logic '1.' note: cmd[2] = 1 signals that the search is a x272-bit search. cmd[8:7] is ignored in this cy- cle. C cycle b: the host asic continues to drive the cmdv high and applies search command ('10') on cmd[1:0]. the dq[67:0] is driven with the 68-bit data ([203:136]) to be compared to all locations '1' in the four 68-bits-word page. C cycle c: the host asic drives the cmdv high and applies search command code ('10') on cmd[1:0] signals. cmd[5:3] signals must be driven with the index to the gmr pair used for the bits [135:0] of the data being searched. cmd[8:7] signals must be driven with the bits that will be driven by this device on sadr[21:20] if it has a hit. dq[67:0] must be driven with the 68-bit data ([135:68]) to be com- pared to all locations 2 in the four 68-bit-word page. the cmd[2] signal must be driven to logic '0.' C cycle d: the host asic continues to drive the cmdv high and continues to apply search command code ('10') on cmd[1:0]. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and the hit flag (see search- successful registers (ssr[0:7]), page 23). the dq[67:0] is driven with the 68-bit data ([67:0]) to be compared to all locations 3 in the four 68- bit-word page. cmd[5:2] is ignored because the learn instruction is not supported for x272 ta- bles. note: for 272-bit searches, the host asic must supply four distinct 68-bit data words on dq[67:0] during cycles a, b, c, and d. the gmr index in cycle a selects a pair of gmrs in each of the 31 devices that apply to dq data in cycles a and b. the gmr index in cycle c se- lects a pair of gmrs in each of the 31 devices that apply to dq data in cycles c and d. the logical 272-bit search operation is as shown in figure 73, page 103. the entire table of 272-bit entries is compared to a 272-bit word k that is presented on the dq bus in cycles a, b, c, and d of the command using the gmr and local mask bits. the gmr is the 272-bit word specified by the two pairs of gmrs selected by the gmr in- dexes in the commands cycles a and c in each of the 31 devices. the 272-bit word k that is pre- sented on the dq bus in cycles a, b, c, and d of the command is compared to each entry in the ta- ble starting at location 0. the first matching en- trys location address, l, is the winning address that is driven as part of the sram address on the sadr[21:0] lines (see sram addressing, page 126). note: the matching address is always going to be location 0 in a four-entry page for 272-bit search (two lsbs of the matching index will be '00'). the search command is a pipelined operation and executes a search at one-fourth the rate of the frequency of clk2x for 272-bit searches in x272- configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 272-bit search command (measured in clk cycles) from the clk2x cycle that contains cycles c and d shown in table 47, page 115. the latency of a search from command to sram access cycle is 6 for only a single device in the table and tlsz = 10. in addition, ssv and ssf shift further to the right for different values of hlat, as specified in table 48, page 115 the 272-bit search operation is pipelined and executes as follows: C four cycles from the last cycle of the search command each of the devices knows the out- come internal to it for that operation. C in the fifth cycle from the search command, the devices in a block (which is less than or equal to eight devices resolving the winner with- in them using an lhi[6:0] and lho[1:0] signal- ling mechanism) arbitrate for a winner. C in the sixth cycle after the search comm and, the blocks of devices resolve the winning block through a bhi[2:0] and bho[2:0] signalling mechanism. the winning device within the win- ning block is the global winning device for the search operation.
101/150 m7020r table 46. hit/miss assumption figure 71. hardware diagram for a table with 31 devices search number 1 2 3 block 0 miss miss miss block 1 miss miss hit block 2 miss hit hit block 3 hit hit miss sram bhi[2] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] block of 8 m7020rs, block 0 (devices 0-7) block of 8 m7020rs, block 1 (devices 8-15) block of 8 m7020rs, block 2 (devices 16-23) block of 7 m7020rs, block 3 (devices 24-30) ai05671 gnd gnd gnd ssf, ssv cmd[8:0], cmdv dq[67:0]
m7020r 102/150 figure 72. hardware diagram for a block of up to eight devices dq[67:0] sram bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bho[2] bho[1] bho[0] bho[2] bho[1] bho[0] lho[1] lho[0] lho[0] lho[1] lho[0] lho[0] lho[0] lho[0] lho[0] lho[1] lho[1] lho[1] lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi 3210 3210 3210 3210 3210 3210 3210 3210 m7020r #0 m7020r #1 m7020r #2 m7020r #3 m7020r #4 m7020r #5 m7020r #6 m7020r #7 lho[0] 654 654 654 654 654 654 654 654 ai05672 cmdv cmd[8:0] ssv, ssf
103/150 m7020r figure 73. x272 table with 31 devices cfg = 10101010 0 4 8 12 262140 (272-bit configuration) location address l 271 0 k gmr 271 0 ai06302 (first matching entry) 0 123 bcd a must be the same in each of 31 devices
m7020r 104/150 timing diagrams for x272 using up to 31 m7020r devices figure 74. each device in block number 0 (miss on each device) note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) ale_l ai06303 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 (lhi[6:0]) (1) bho[2:0] (4) (bhi[2:0]) (3) search3 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 10101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 01 01 01 z z 0 0 0 0 z z z z z
105/150 m7020r figure 75. each device above the winning device in block number 1 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) ale_l ai06303 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 (lhi[6:0]) (1) bho[2:0] (4) (bhi[2:0]) (3) search3 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 10101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 01 01 01 z z 0 0 0 0 z z z z z
m7020r 106/150 figure 76. globally winning device in block number 1 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) ale_l ai06304 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 a3 (lhi[6:0]) (1) bho[2:0] (4) (bhi[2:0]) (3) search3 (this device global winner.) search1 (miss on this device.) search2 (miss on this device.) cfg = 10101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 01 01 01 0 0 0 0 z z z z z 0 0 1 1 1 z z
107/150 m7020r figure 77. devices below the winning device in block number 1 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) ale_l ai06305 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 (lhi[6:0]) (1) bho[2:0] (4) (bhi[2:0]) (3) search3 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 10101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 01 01 01 0 0 0 0 z z z z z z z
m7020r 108/150 figure 78. devices above the winning device in block number 2 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) ale_l ai06306 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 (lhi[6:0]) (1) bho[2:0] (4) (bhi[2:0]) (3) search3 (miss on this device; hit in block 0 or 1.) search1 (miss on this device.) search2 (miss on this device.) cfg = 10101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 01 01 01 0 0 0 0 z z z z z z z
109/150 m7020r figure 79. globally winning device in block number 2 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) ale_l ai06307 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 a2 (lhi[6:0]) (1) bho[2:0] (4) (bhi[2:0]) (3) search3 (hit but not a winner.) search1 (miss on this device.) search2 (global winner.) cfg = 10101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 01 01 01 0 0 0 0 z z z z z z z z z z z z z z 0 0 1 1 1 z z
m7020r 110/150 figure 80. devices below the winning device in block number 2 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) ale_l ai06308 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 (lhi[6:0]) (1) bho[2:0] (4) (bhi[2:0]) (3) search3 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 10101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 01 01 01 0 0 0 0 z z z z z z z
111/150 m7020r figure 81. devices above the winning device in block number 3 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) ale_l ai06309 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 (lhi[6:0]) (1) bho[2:0] (4) (bhi[2:0]) (3) search3 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 10101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 01 01 01 0 0 0 0 z z z z z z z
m7020r 112/150 figure 82. globally winning device in block number 3 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) ale_l ai06310 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 a1 (lhi[6:0]) (1) bho[2:0] (4) (bhi[2:0]) (3) search3 (miss on this device.) search1 (global winner.) search2 (hit but not a global winner.) cfg = 10101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 01 01 01 0 0 0 0 z z z z z z z z z z z 0 0 1 1 1 z z
113/150 m7020r figure 83. devices below the winning device in block number 3 (not device 30 - last device) note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) ale_l ai06311 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 (lhi[6:0]) (1) bho[2:0] (4) (bhi[2:0]) (3) search3 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 10101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 01 01 01 0 0 0 0 z z z z z z z
m7020r 114/150 figure 84. last device in block number 3 (device 30 in the table) note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l lho[1:0] (2) ale_l ai06312 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 (lhi[6:0]) (1) bho[2:0] (4) (bhi[2:0]) (3) search3 (hit on some device above.) search1 (hit on some device above.) search2 (hit on some device above.) cfg = 10101010, hlat = 000, tlsz = 10, lram = 1, ldev = 1 search1 search2 search3 01 01 01 0 0 0 0 z z z z z z z z z z z z z z z z z 00 0 0 0 0 0 0 1 1 z z
115/150 m7020r table 47. latency of search from cycles c and d to sram access cycle, 272-bit, up to 31 devices table 48. shift of ssf and ssv from sadr mixed searches tables configured with different widths using an m7020r the sample operation shown is for a single device with cfg = 1001000. it contains three tables of x68, x136, and x272 widths. the operation may be generalized to a block of 8C31 devices using four blocks; the timing and the pipeline operation is the same as described previously for fixed searches on a table of one-width-size. figure 85, page 116 shows three sequential searches: C a 68-bit search on the table configured as x68; C a 136-bit search on a table configured as x136; and C a 272-bit search on the table configured as x272 bits that each results in a hit. note: the dq[67:66] will be '00' in both of the cy- cles a and b of the x68-bit search (search1). dq[67:66] is '01' in both of the cycles a and b of the x136-bit search (search2). dq[67:66] is '10' in all of the cycles a, b, c, and d of the x272-bit search (search 3). by having table designation bits, the m7020r enables the creation of many ta- bles in a bank of search engines of different widths. figure 86, page 117 shows the sample table. two bits in each 68-bit entry will need to designated as the table number bits. one example choice can be the '00' values for the table configured as x68, '01' values for tables configured as x136, and '10' values for tables configured as x272. for the above explanation, it is further assumed that bits [67:66] for each entry will be designed as these table designation bits. # of devices max table size latency in clk cycles 1 (tlsz = 00) 8k x 272-bit 4 2C8 (tlsz = 01) 64k x 272-bit 5 9C31 (tlsz = 10) 248k x 272-bit 6 hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
m7020r 116/150 figure 85. timing diagram for mixed search for one device cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[21:0] ssv ssf cmd[8:2] phs_ l ale_l ai06313 a b a b a b a b a b a b a b c d dq d1 d2 d3 a3 a2 a1 search3 (x272 hit) search1 (x68 hit) search2 (x136 hit) cfg = 10010000, hlat = 010, tlsz = 00, lram = 1, ldev = 1 search1 search2 search3 01 01 01 1 01 01 1 1 01 01 1 0 1 0 1 0 1 0 11 0 00 0 0
117/150 m7020r figure 86. multi-width configurations example lram and ldev description when search engines are cascaded using multiple m7020rs, the sadr, ce_l, and we_l (3-state signals) are all tied together. in order to eliminate external pull-up and pull-downs, one device in a bank is designated as the default driver. for non- search or non-learn cycles (see learn command in the section below) or search cycles with a global miss, the sadr, ce_l, and we_l signals are driven by the device with the lram bit set. note: it is important that only one device in a bank of search engines that are cascaded have this bit set. failure to do so will cause contention on sadr, ce_l, we_l, and can potentially cause damage to the device(s). similarly, when search engines using multiple m7020rs are cascaded, ssf and ssv (also 3- state signals) are tied together. in order to elimi- nate external pull-up and pull-downs, one device in a bank is designated as the default driver. for non-search cycles or search cycles with a global miss the ssf and ssv signals are driven by the device with the ldev bit set. note: it is important that only one device in a bank of search engines that are cascaded together have this bit set. failure to do so will cause conten- tion on ssv and ssf and can potentially cause damage to the device(s). 16 k 4 k 2 k 68 136 272 cfg = 10 01 00 00 ai06314
m7020r 118/150 learn command bit [0] of each 68-bit data location specifies wheth- er an entry in the database is occupied. if all the entries in a device are occupied, the device as- serts fulo signal to inform the downstream de- vices that it is full. the result of this communication between depth- cascaded devices determines the global full signal for the entire table. the full signal in the last device determines the fullness of the depth- cascaded table. in a depth-cascaded table, only a single device will learn the entry through the application of a learn instruction. the determination of which device is going to learn is based on the fuli and fulo sig- nalling between the devices. the first non-full de- vice learns the entry by storing the contents of the specified comparand registers to the location(s) pointed to by nfa. in a x68-configured table the learn command writes a single 68-bit location. in a x136-config- ured table the learn command writes the next even and odd 68-bit locations. in 136-bit mode, bit[0] of the even and odd 68-bit locations is '0,' which indicates they are cascaded empty, or '1,' which indicates they are occupied. the global full signal indicates to the table con- troller (the host asic) that all entries within a block are occupied and that no more entries can be learned. the m7020r updates the signal after each write or learn command to a data array. the learn command generates a write cycle to the external sram, also using the nfa register as part of the sram address (see sram ad- dressing, page 126). the learn command is supported on a single block containing up to eight devices if the table is configured either as a x68 or a x136. the learn command is not supported for x272-configured ta- bles. learn is a pipelined operation and lasts for two clk cycles, as shown in figure 87, page 119 where tlsz = 00, and figure 88, page 120 and figure 89, page 121 where tlsz = 01 (which as- sume the device performing the learn operation is not the last device in the table and has its lram bit set to '0.' note: the oe_l for the device with the lram bit set goes high for two cycles for each learn (one during the sram write cycle, and one the cycle before). the latency of the sram write cycle from the second cycle of the instruction is shown in table 49, page 121. the sequence of operation is as follows: C cycle 1a : the host asic applies the learn in- struction on the cmd[1:0], using cmdv = 1. the cmd[5:2] field specifies the index of the comparand register pair that will be written in the data array in the 136-bit-configured table. for a learn in a 68-bit-configured table, the even-numbered comparands specified by this index will be written. cmd[8:7] carries the bits that will be driven on sadr[21:20] in the sram write cycle. C cycle 1b : the host asic continues to drive cmdv to '1,' cmd[1:0] to '11,' and cmd[5:2] with the comparand pair index. cmd[6] must be set to '0' if the learn is being performed on a 68-bit-configured table, and to '1' if the learn is being performed on a 136-bit-configured ta- ble. C cycle 2: the host asic drives the cmdv to '0.' at the end of cycle 2, a new instruction can be- gin. the latency of the sram write is the same as the search to the sram read cycle. it is measured from the second cycle of the learn instruction.
119/150 m7020r figure 87. timing diagram of learn: tlsz = 00 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l ssv ssf sadr[21:0] cmd[8:2] phs_ l ai06315 dq a1 a2 tlsz = 00, lram = 1, ldev = 1 learn1 learn2 comp1 1a 1b comp2 x x x x x x x x 1 1 0 0 0 1 0 0 1 0 0 1 0 z
m7020r 120/150 figure 88. timing diagram of learn: tlsz = 01 (except on the last device) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l ssv ssf sadr[21:0] cmd[8:2] phs_ l ai06316 dq a1 tlsz = 01, lram = 0, ldev = 0 learn1 learn2 comp1 1a 1b comp2 x x x x x x x x z z z z z z z z z 0 0 0 0 z a2
121/150 m7020r figure 89. timing diagram of learn on device 7: tlsz = 01 table 49. latency of sram write cycle from second cycle of learn instruction # of devices latency in clk cycles 1 (tlsz = 00) 4 2C8 (tlsz = 01) 5 9C31 (tlsz = 10) 6 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l ssv ssf sadr[21:0] cmd[8:2] phs_ l ai06317 dq tlsz = 01, lram = 1, ldev = 1 learn1 learn2 comp1 1a 1b comp2 x x x x x x x x 1 1 0 0 0 z z 1 1 1 z z 1 z 0 1 z z
m7020r 122/150 depth-cascading the search engine application can depth-cascade the device to various table sizes of different widths (e.g., 68-bit, 136-bit, and 272-bit configurations). the devices perform all the necessary arbitration to decide which device drives the sram bus. the latency of the searches increases as the table size increases while the search rate remains constant. depth-cascading up to eight devices (one block) figure 90, page 123 shows how up to eight devic- es can cascade to form a 256k x68, 128k x136, or 64k x272 bit table. it also shows the interconnec- tion between the devices for depth-cascading. each search engine asserts the lho[1] and lho[0] signals to inform downstream devices of its result. the lhi[6:0] signals for a device are con- nected to lho signals of the upstream devices. the host asic must program the tlsz to '01' for each of up to eight devices in a block. only a single device drives the sram bus in any single cycle. depth-cascading up to 31 devices (4 blocks) figure 91, page 124 shows how to cascade up to four blocks. each block contains up to eight m7020rs (except the last block) and the intercon- nection within each is shown in figure 90, page 123. note: the interconnection between blocks for depth-cascading is important. for each search, a block asserts bho[2], bho[1], and bho[0]. the bho[2:0] signals for a block are the signals taken only from the last device in the block. for all other devices within that block, these signals stay open and floating. the host asic must program the ta- ble size (tlsz) field to '10' in each of the devices for cascading up to 31 devices (in up to four blocks). depth-cascading to generate a full signal bit[0] of each of the 68-bit entries is designated as a special bit (1 = occupied; 0 = empty). for each learn or pio write to the data array, each de- vice asserts fulo[1] and fulo[0] if it does not have any empty locations (see figure 92, page 125). each device combines the fulo signals from the devices above it with its own full status to gener- ate a full signal that gives the full status of the table up to the device asserting the full signal. figure 92, page 125 shows the hardware connec- tion diagram for generating the full signal that goes back to the asic. in a depth-cascaded block of up to eight devices, the full signal from the last device should be fed back to the asic control- ler to indicate the fullness of the table. the full signal of the other devices should be left open. note: the learn instruction is supported for only up to eight devices, whereas full cascading is allowed only for one block in tables containing more than eight devices. in tables for which a learn instruction is not going to be used, the bit[0] of each 68-bit entry should always be set to '1.'
123/150 m7020r figure 90. depth-cascading to form a single block sram bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bho[2] bho[1] bho[0] bho[2] bho[1] bho[0] lho[1] lho[0] lho[0] lho[1] lho[0] lho[0] lho[0] lho[0] lho[0] lho[1] lho[1] lho[1] lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi 3210 3210 3210 3210 3210 3210 3210 3210 m7020r #0 m7020r #1 m7020r #2 m7020r #3 m7020r #4 m7020r #5 m7020r #6 m7020r #7 lho[0] 654 654 654 654 654 654 654 654 ai05666 ssf, ssv dq[67:0] cmdv cmd[8:0]
m7020r 124/150 figure 91. depth-cascading four blocks sram bhi[2] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] block of 8 m7020rs, block 0 (devices 0-7) block of 8 m7020rs, block 1 (devices 8-15) block of 8 m7020rs, block 2 (devices 16-23) block of 7 m7020rs, block 3 (devices 24-30) ai05671 gnd gnd gnd ssf, ssv cmd[8:0], cmdv dq[67:0]
125/150 m7020r figure 92. full generation in a cascaded table dq[71:0] fulo[1] fulo[0] fulo[0] fulo[1] fulo[0] fulo[0] fulo[0] fulo[0] fulo[0] fulo[1] fulo[1] fulo[1] fuli fuli fuli fuli fuli fuli fuli fuli fuli fuli fuli 3210 3210 3210 3210 3210 3210 3210 3210 m7020r m7020r m7020r m7020r m7020r m7020r m7020r m7020r fulo[0] 654 654 654 654 654 654 654 654 ai06318 full full full full full full full full v ddq v ddq v ddq v ddq v ddq v ddq v ddq
m7020r 126/150 sram addressing table 50, page 127 describes the commands used to generate addresses on the sram address bus. the index [14:0] field contains the address of a 68- bit entry that results in a hit in 68-bit-configured quadrant. it is the address of the 68-bit entry that lies at the 136-bit page, and the 272-bit page boundaries in 136-bit- and 272-bit-configured quadrants, respectively. registers, page 21 of this specification, de- scribes the nfa and ssr registers. adr[14:0] contains the address supplied on the dq bus dur- ing pio access to the m7020r. command bits 8 and 7 {cmd[8:7]} are passed from the command to the sram address bus (see command codes and parameters, page 29 for more information). id[4:0] is the id of the device driving the sram bus (see figure 3, page 10 and table 2, page 9 for more information). sram pio access sram read enables read access to off-chip sram that contains associative data. the latency from the issuance of the read instruction to the address appearing on the sram bus is the same as the latency of the search instruction and will depend on the tlsz value parameter pro- grammed in the device configuration register. the latency of the ack from the read instruction is the same as the latency of the search instruc- tion to the sram address plus the hlat pro- grammed in the configuration register. note: sram read is a blocking operation C no new instruction can begin until the ack is returned by the selected device performing the access. sram write enables write access to the off- chip sram containing associative data. the laten- cy from the second cycle of the write instruction to the address appearing on the sram bus is the same as the latency of the search instruction and will depend on the tlsz value parameter pro- grammed in the device configuration register. note: sram write is a pipelined operation C new instruction can begin right after the previous command has ended. sram read with a table of one device sram read enables read access to the off- chip sram containing associative data. the laten- cy from the issuance of the read instruction to the address appearing on the sram bus is the same as the latency of the search instruction and will depend on the tlsz value parameter pro- grammed in the device configuration register. the latency of the ack from the read instruction is the same as the latency of the search instruc- tion to the sram address plus the hlat pro- grammed in the configuration register. the following explains the sram read operation in a table with only one device that has the follow- ing parameters: tlsz = 00, hlat = 000, lram = 1, and ldev = 1. figure 93, page 127 shows the associated timing diagram. for the following description, the selected device refers to the only device in the table because it is the only device to be accessed. the sequence of the operation is as follows: C cycle 1a: the host asic applies the read in- struction on the cmd[1:0], using cmdv = 1. the dq bus supplies the address with dq[20:19] set to '10' to select the sram ad- dress. the host asic selects the device for which the id[4:0] matches the dq[25:21] lines. during this cycle, the host asic also supplies sadr[21:20] on cmd[8:7] in this cycle. C cycle 1b: the host asic continues to apply the read instruction on the cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to '10' to select the sram address. C cycle 2: the host asic floats dq[67:0] to a 3- state condition. C cycle 3: the host asic keeps dq[67:0] in a 3- state condition. C cycle 4: the selected device starts to drive dq[67:0] and drives ack from high-z to low. C cycle 5: the selected device drives the read address on sadr[21:0]; it also drives ack high, ce_l low, and ale_l low. C cycle 6: the selected device drives ce_l high, ale_l high, the sadr bus, and the dq bus in a 3-state condition; it drives ack low. at the end of cycle 6, the selected device floats ack in a 3-state condition, and a new command can begin.
127/150 m7020r table 50. generating an sram bus address figure 93. sram read access for one device command sram operation 21 20 [19:15] [14:0] search read c8 c7 id[4:0] index[14:0] learn write c8 c7 id[4:0] nfa[14:0] pio read read c8 c7 id[4:0] adr[14:0] pio write write c8 c7 id[4:0] adr[14:0] indirect access write/read c8 c7 id[4:0] ssr[14:0] cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 clk2x cmdv cmd[1:0] ack ssv ssf sadr dq oe_l we_l ce_l phs_ l ai06319 read cmd[8:2] ab address ad dress (dq driven by m7040) hlat = 000, tlsz = 00, lram = 1, ldev = 1 z z 0 1 1 ale_l 1 z 0 0 0 0 1 1 0 1 0 z
m7020r 128/150 sram read with a table of up to eight devices the following explains the sram read operation completed through a table of up to eight devices using the following parameters: tlsz = 01. figure 94, page 129 diagrams a block of eight devices. the following assumes that sram access is suc- cessfully achieved through m7020r device 0. fig- ure 95, page 130 and figure 96, page 131 show timing diagrams for device 0 and device 7, re- spectively. C cycle 1a: the host asic applies the read in- struction on the cmd[1:0] using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to '10' to select the sram address. the host asic selects the device for which id[4:0] match- es the dq[25:21] lines. during this cycle the host asic also supplies sadr[21:20] on cmd[8:7]. C cycle 1b: the host asic continues to apply the read instruction on the cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to '10' to select the sram address. C cycle 2: the host asic floats dq[67:0] to a 3- state condition. C cycle 3: the host asic keeps dq[67:0] in a 3- state condition. C cycle 4: the selected device starts to drive dq[67:0]. C cycle 5: the selected device continues to drive dq[67:0] and drives ack from high-z to low C cycle 6: the selected device drives the read address on sadr[21:0]. it also drives ack high, ce_l low, we_l high, and ale_l low. C cycle 7: the selected device drives ce_l, ale_l, we_l, and the dq bus in a 3-state con- dition. it continues to drive ack low. at the end of cycle 7, the selected device floats ack in 3-state condition and a new command can begin.
129/150 m7020r figure 94. table with eight devices sram bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bho[2] bho[1] bho[0] bho[2] bho[1] bho[0] lho[1] lho[0] lho[0] lho[1] lho[0] lho[0] lho[0] lho[0] lho[0] lho[1] lho[1] lho[1] lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi 3210 3210 3210 3210 3210 3210 3210 3210 m7020r #0 m7020r #1 m7020r #2 m7020r #3 m7020r #4 m7020r #5 m7020r #6 m7020r #7 lho[0] 654 654 654 654 654 654 654 654 ai05666 ssf, ssv dq[67:0] cmdv cmd[8:0]
m7020r 130/150 figure 95. sram read through device 0 in a block of eight devices cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 clk2x cmdv cmd[1:0] ack ssv ssf sadr dq oe_l we_l ce_l phs_ l ai06320 read cmd[8:2] ab address ad dress (dq driven by the selected m7040) hlat = 000, tlsz = 01, lram = 0, ldev = 0 z z z z z ale_l z z z z z 0 0 z z 1 z 0 1 0
131/150 m7020r figure 96. sram read timing for device 7 in a block of eight devices cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 clk2x cmdv cmd[1:0] ack ssv ssf sadr dq oe_l we_l ce_l phs_ l ai06321 read cmd[8:2] ab ad dress hlat = 000, tlsz = 01, lram = 0, ldev = 0 z 0 1 1 ale_l 1 z z z z z z 1 1 z 1
m7020r 132/150 sram read with a table of up to 31 devices the following explains the sram read operation accomplished through a table of up to 31 devices, using the following parameters: tlsz = 10. the di- agram of such a table is shown in figure 97, page 133. the following assumes that sram access is being accomplished through m7020r device 0 and that device 0 is the selected device. figure 98, page 134 and figure 99, page 135 show the timing dia- grams for device 0 and device 30, respectively. C cycle 1a: the host asic applies the read in- struction to cmd[1:0] using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to '10,' to select the sram address. the host asic selects the device for which the id[4:0] matches the dq[25:21] lines. during this cycle, the host asic also supplies sadr[21:20] on cmd[8:7]. C cycle 1b: the host asic continues to apply the read instruction to cmd[1:0] using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to '10,' to select the sram ad- dress. C cycle 2: the host asic floats dq[67:0] to a 3- state condition. C cycle 3: the host asic keeps dq[67:0] in a 3- state condition. C cycle 4: the selected device starts to drive dq[67:0]. C cycles 5 to 6: the selected device continues to drive dq[67:0]. C cycle 7: the selected device continues to drive dq[67:0] and drives an sram read cycle. C cycle 8: the selected device drives acl from z to low. C cycle 9: the selected device drives ack to high. C cycle 10: the selected device drives ack from high to low. at the end of cycle 10, the selected device floats acl in a 3-state condition.
133/150 m7020r figure 97. table of 31 devices made of four blocks sram bhi[2] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] block of 8 m7020rs, block 0 (devices 0-7) block of 8 m7020rs, block 1 (devices 8-15) block of 8 m7020rs, block 2 (devices 16-23) block of 7 m7020rs, block 3 (devices 24-30) ai05671 gnd gnd gnd ssf, ssv cmd[8:0], cmdv dq[67:0]
m7020r 134/150 figure 98. sram read through device 0 in a bank of 31 devices (device 0 timing) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[8:2] ce_l we_l oe_l sadr[21:0] ssv ack ssf phs_ l ale_l ai06322 dq driven by the selected m7040 dq hlat = 010, tlsz = 01, lram = 0, ldev = 0 read address address 00 ab z 0 z 0 z 0 z z z 0 1 z 1 z z z z z z
135/150 m7020r figure 99. sram read through device 0 in a bank of 31 devices (device 30 timing) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[8:2] ce_l we_l oe_l sadr[21:0] ssv ack ssf phs_ l ale_l ai06323 dq hlat = 010, tlsz = 01, lram = 1, ldev = 1 read address 00 ab 1 z 1 z 1 1 1 z 1 z 0 0 0 z
m7020r 136/150 sram write with a table of one device sram write enables write access to the off- chip sram that contains associative data. the la- tency from the second cycle of the write instruc- tion to the address appearing on the sram bus is the same as the latency of the search instruc- tion, and will depend on the tlsz value parameter programmed in the device configuration register. the following explains the sram write opera- tion accomplished with a table of only one device of the following parameters: tlsz = 00, hlat = 000, lram = 1, and ldev = 1. figure 100, page 137 shows the timing diagram. for the following description the selected device refers to the only device in the table as it is the only device that will be accessed. C cycle 1a: the host asic applies the write in- struction on cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to '10' to select the sram address. the host asic selects the device for which the id[4:0] matches the dq[25:21] lines. the host asic also sup- plies sadr[21:20] on cmd[8:7] in this cycle. note: cmd[2] must be set to '0' for sram write because burst writes into the sram are not supported. C cycle 1b: the host asic continues to apply the write instruction on cmd[1:0], using cmdv = 1. the dq bus supplies the address with dq[20:19] set to '10' to select the sram address. note: cmd[2] must be set to '0' for sram write because burst writes into the sram are not supported. C cycle 2: the host asic continues to drive dq[67:0]. the data in this cycle is not used by the m7020r device. C cycle 3: the host asic continues to drive dq[67:0]. the data in this cycle is not used by the m7020r device. at the end of cycle 3, a new command can begin. the write is a pipelined operation. the write cycle appears at the sram bus, however, with the same latency as that of a search instruction, as measured from the second cycle of the write command.
137/150 m7020r figure 100. sram write access for one device cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 clk2x cmdv cmd[1:0] ack ssv ssf sadr dq oe_l we_l ce_l phs_ l ai06324 cmd[8:2] a write b address ad dress hlat = 000, tlsz = 00, lram = 1, ldev = 1 0 1 1 ale_l 1 z 0 0 0 0 0 1 x x
m7020r 138/150 sram write with a table of up to eight devices the following explains the sram write opera- tion done through a table(s) of up to eight devices with the following parameters (tlsz = 01). the di- agram of such a table is shown in figure 101, page 139. the following assumes that sram access is done through m7020r device 0. figure 102, page 140 and figure 103, page 141 show the timing dia- gram for device 0 and device 7, respectively. C cycle 1a: the host asic applies the write in- struction on cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to '10' to select the sram address. the host asic selects the device for which the id[4:0] matches the dq[25:21] lines. the host asic also sup- plies sadr[23:21] on cmd[8:6] in this cycle. note: cmd[2] must be set to '0' for sram write because burst writes into the sram are not supported. C cycle 1b: the host asic continues to apply the write instruction on cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to '10' to select the sram ad- dress. note: cmd[2] must be set to '0' for sram write because burst writes into the sram are not supported. C cycle 2: the host asic continues to drive dq[67:0]. the data in this cycle is not used by the m7020r device. C cycle 3: the host asic continues to drive dq[67:0]. the data in this cycle is not used by the m7020r device. at the end of cycle 3, a new command can begin. the write is a pipelined operation. the write cycle appears at the sram bus, however, with the same latency as that of a search instruction, as measured from the second cycle of the write command.
139/150 m7020r figure 101. table with eight devices sram bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bho[2] bho[1] bho[0] bho[2] bho[1] bho[0] lho[1] lho[0] lho[0] lho[1] lho[0] lho[0] lho[0] lho[0] lho[0] lho[1] lho[1] lho[1] lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi 3210 3210 3210 3210 3210 3210 3210 3210 m7020r #0 m7020r #1 m7020r #2 m7020r #3 m7020r #4 m7020r #5 m7020r #6 m7020r #7 lho[0] 654 654 654 654 654 654 654 654 ai05666 ssf, ssv dq[67:0] cmdv cmd[8:0]
m7020r 140/150 figure 102. sram write through device 0 in a block of eight devices cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[8:2] ce_l we_l oe_l sadr[21:0] ssv ack ssf phs_ l ale_l ai06325 dq hlat = xxx, tlsz = 01, lram = 0, ldev = 0 write address address 01 ab z 0 z 0 z z z z z z 0 z x x z z z z
141/150 m7020r figure 103. sram write timing for device 7 in a block of eight devices cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[8:2] ce_l we_l oe_l sadr[21:0] ssv ack ssf phs_ l ale_l ai06326 dq hlat = xxx, tlsz = 01, lram = 1, ldev = 1 write address 01 ab 1 z 1 z 1 1 1 z 1 0 1 z 0 0 0 z x x
m7020r 142/150 sram write with table(s) of up to 31 devices the following explains the sram write opera- tion done through a table(s) of up to 31 devices with the following parameters (tlsz = 10). the di- agram of such table(s) is shown in figure 104, page 143. the following assumes that sram ac- cess is done through m7020r device 0 C device 0 is the selected device. figure 105, page 144 and figure 106, page 145 show the timing diagram for device 0 and device 30, respectively. C cycle 1a: the host asic applies the write in- struction on cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to '10' to select the sram address. the host asic selects the device for which the id[4:0] matches the dq[25:21] lines. the host asic also sup- plies sadr[21:20] on cmd[8:7] in this cycle. note: cmd[2] must be set to '0' for sram write because burst writes into the sram are not supported. C cycle 1b: the host asic continues to apply the write instruction on cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to '10' to select the sram ad- dress. note: cmd[2] must be set to '0' for sram write because burst writes into the sram are not supported. C cycle 2: the host asic continues to drive dq[67:0]. the data in this cycle is not used by the m7020r device. C cycle 3: the host asic continues to drive dq[67:0]. the data in this cycle is not used by the m7020r device. at the end of cycle 3, a new command can begin. the write is a pipelined operation. the write cycle appears at the sram bus, however, with the same latency as that of a search instruction, as measured from the second cycle of the write command
143/150 m7020r figure 104. table of 31 devices (four blocks) sram bhi[2] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] block of 8 m7020rs, block 0 (devices 0-7) block of 8 m7020rs, block 1 (devices 8-15) block of 8 m7020rs, block 2 (devices 16-23) block of 7 m7020rs, block 3 (devices 24-30) ai05671 gnd gnd gnd ssf, ssv cmd[8:0], cmdv dq[67:0]
m7020r 144/150 figure 105. sram write through device 0 in a bank of 31 devices (device 0 timing) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[8:2] ce_l we_l oe_l sadr[21:0] ssv ack ssf phs_ l ale_l ai06327 dq hlat = xxx, tlsz = 10, lram = 0, ldev = 0 write address address 01 ab z 0 z 0 z z z z z z 0 z x x z z z z
145/150 m7020r figure 106. sram write through device 0 in a bank of 31 devices (device 30 timing) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[8:2] ce_l we_l oe_l sadr[21:0] ssv ack ssf phs_ l ale_l ai06328 dq hlat = xxx, tlsz = 10, lram = 1, ldev = 1 write address 01 ab 1 z 1 z 1 1 1 z 1 1 z 0 0 0 z x x
m7020r 146/150 jtag (1149.1) testing the m7020r supports the test access port and boundary scan architecture as specified in the ieee jtag sta ndard 1149.1. the pin interface to the chip consists of five signals with the standard definitions: tck, tms, tdi, tdo, and trst_l. table 51 describes the operations that the test ac- cess port controller supports and table 52 de- scribes the tap device id register. note: to disable jtag functionality, connect the tck, tms, and tdi pins to ground, and trst_l to v dd . table 51. supported operations table 52. tap device id register instruction type description sample/preload mandatory sample/preload. loads the values of signals going to and from io pins into the boundary scan shift register to provide a snapshot of the normal functional operation. extest mandatory external test. uses boundary scan values shifted in from tap to test connectivity external to the device. intest optional internal test. allows slow-speed, functional testing of the device using the boundary scan register to provide the i/o values. field range initial value description revision [31:28] 0001 revision number. this is the current device revision number. numbers start from one and increment by one for each revision of the device. part # [27:12] 0000 0000 0000 0001 this is the part number for this device. mfid [11:1] 000_1101_1100 manufacturer id. this field is the same as the manufacturer id used in the tap controller. lsb [0] 1 least significant bit
147/150 m7020r part numbering table 53. ordering information scheme note: 1. where z is the symbol for bga packages and a denotes 1.27mm ball pitch for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: m70 20 r C083 za 1 t device type m70 search engine density 20 = 2mb (32k x 68-bit table entries) operating supply voltage r = v dd = 1.8v speed C083 = 83 million searches per second C066 = 66 million searches per second C050 = 50 million searches per second package pbga = 272-ball count, 27mm x 27mm (1) , 1.27mm ball pitch temperature range 1 = 0 to 70c shipping optio n tape & reel packing = t
m7020r 148/150 package mechanical information figure 107. pbga-z00 C 272-ball plastic ball grid array package outline note: drawing is not to scale. table 54. pbga-z00 C 272-ball plastic ball grid array package mechanical data note: 1. maximum mounted height is 2.45mm based on a 0.65mm ball pad diameter. solder paste is 0.15mm thickness and 0.65mm in di- ameter. 2. the terminal a1 corner must be identified on the top surface by using a corner chamfer, ink, or metallized markings, or other feature of package body or integral heatslug. 3. a distinguished feature is allowable on the bottom surface of the package to identify the terminal a1 corner. 4. exact shape of each corner is optional. symb mm inches typ min max typ min max a (4) 27.00 26.80 27.20 (1) 1.102 1.094 1.110 (1) a1 (2,3) 0.60 0.50 0.70 0.024 0.020 0.029 a2 1.63 1.90 0.067 0.078 b (4) 27.00 26.80 27.20 1.102 1.094 1.110 b 0.75 0.60 0.90 0.031 0.024 0.037 d 27.00 26.80 27.20 1.102 1.094 1.110 d1 24.13 0.985 d2 24.00 0.980 e 1.27 0.052 e 27.00 26.80 27.20 1.102 1.094 1.110 e1 24.13 0.985 e2 24.00 0.980 n 272 272 ddd 0.20 0.008 eee 0.30 0.012 a2 a1 1.17 ref. 0.56 ref. e2 pin #1 d2 ddd c 0.220 (3x) c b a e e e e1 b d1 d 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y 0.300 c 0.100 c s a b s pbga-z00 4.00*45? (4x) 30? typ. b (272x)
149/150 m7020r revision history table 55. document revision history date revision details february 2001 first issue 03/23/01 document re-organization, change in power distribution text 04/02/01 updated mechanical drawing and table (figure 107, table 54) 07/23/01 routine maintenance (based on recent data sheet review findings) 10/02/01 change references to lara and st to cypress in description section; added 83mhz speed grade to document; values, references, and footnotes changed (table 3, 4, 5, 6, 7, 54); labels changed (figures 5, 8); basic formatting changes based on recent reviews 11/14/01 rework document (add graphics, change text) after cypress purchase
m7020r 150/150 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2001 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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